Fujitsu MB90460 Series, Hardware Manual, Page: 284 / 739

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CHAPTER 13 16-BIT PPG TIMER
13.4.2 PPG Period Setting Buffer Register (PCSR0 to PCSR2)
PPG period setting buffer register is used to set the period of the output pulses
generated by PPG.
■
PPG Period Setting Buffer Register (PCSR0 to PCSR2)
Figure 13.4-3 PPG Period Setting Buffer Register (PCSR0 to PCSR2)
These are 16-bit registers that are used to set the period of the output pulses generated by PPG. The initial
value of them are undetermined, so that these registers must be written before starting an operation. Word
access to these registers are recommended. These registers are write-only.
Data transfer from period setting buffer register to period setting register will be at counter borrow or
trigger or retrigger if enabled.
Note:
In case of updating period setting buffer register, duty setting buffer register must be written after
writing to period setting buffer register. Only updating period setting buffer register is prohibited.
15 14 13 12 11 10 9 8
PPG Period Setting Buffer Register (Upper)
7 6 5 4 3 2 1 0
PPG Period Setting Buffer Register (Lower)
Address: ch.0 00003B
H
ch.1 000043
H
ch.3 00004B
H
PCSR0 to
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
Initial value
Read/write
Address: ch.0 00003A
H
ch.1 000042
H
ch.3 00004A
H
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
Initial value
Read/write
PCSR0 to
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
PCSR2
PCSR2
bit
bit