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CHAPTER 9 I/O PORT
●
Port operation after a reset
•
When the CPU is reset, the DDR1 and RDR registers are initialized to "0". As a result, the output buffer
is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins are placed in a high
impedance state.
•
The PDR1 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR1 register after the output data is set in the PDR1 register.
●
Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a high-
impedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR1 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Note also that when a pull-up resistor is selected, the port pins are held at the high level and not placed in a
high-impedance state even when the SPL bit is set to "1". Table 9.4-4 lists the states of the port 1 pins.
Table 9.4-4 States of Port 1 Pins
Pin
Normal operation
Sleep mode
Stop mode or time-base
timer mode
(SPL = 0)
Stop mode or time-base
timer mode
(SPL = 1, RDR = 0)
Stop mode or time-base
timer mode
(SPL = 1, RDR = 1)
P10/INT0/
DTTI0 to P17/
FRCK
General-purpose
I/O port
General-purpose
I/O port
General-purpose I/O port
Input enabled*/output in
Hi-Z
Input shut down/held at H
level
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
*
: Only when P10/INT0 to P16/INT6 is configured as external interrupt pins, otherwise input shutdown
Summary of Contents for MB90460 Series
Page 1: ...The following document contains information on Cypress products ...
Page 3: ......
Page 5: ......
Page 9: ...iv ...
Page 41: ...22 CHAPTER 1 OVERVIEW ...
Page 45: ...26 CHAPTER 2 NOTES ON HANDLING DEVICES ...
Page 83: ...64 CHAPTER 3 CPU ...
Page 95: ...76 CHAPTER 4 RESET ...
Page 107: ...88 CHAPTER 5 CLOCK ...
Page 131: ...112 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 175: ...156 CHAPTER 7 INTERRUPT ...
Page 181: ...162 CHAPTER 8 MODE SETTING ...
Page 223: ...204 CHAPTER 9 I O PORT ...
Page 237: ...218 CHAPTER 10 TIME BASE TIMER ...
Page 247: ...228 CHAPTER 11 WATCHDOG TIMER ...
Page 275: ...256 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 373: ...354 CHAPTER 14 MULTI FUNCTIONAL TIMER ...
Page 485: ...466 CHAPTER 16 PWC Timer ...
Page 531: ...512 CHAPTER 17 UART ...
Page 559: ...540 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ...
Page 589: ...570 CHAPTER 20 8 10 BIT A D CONVERTER ...
Page 601: ...582 CHAPTER 21 ROM CORRECTION FUNCTION ...
Page 633: ...614 CHAPTER 23 512K 1024K BIT FLASH MEMORY ...
Page 645: ...626 CHAPTER 24 EXAMPLE OF F2 MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING ...
Page 715: ...696 APPENDIX ...
Page 716: ...697 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 739: ......