Arteche smART P500, Instruction Manual

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4BRELAY SETTINGS
0BDEVICE CONFIGURATION
The final results of the logics are represented in the software as rL + the logic number.
These results can be used as input signals for other gates; this enables the nesting of
the programmable logics. In order to avoid a cycle without output in the evaluation of the
logics, the software applies a validation system to eliminate infinite recursions.
3.4.4.1. EDGE DETECTORS
The upper part shows a set of buttons which activate the
following functions: input negation, falling and rising edge detection to
activate/deactivate, input deletion and function validation.
3.4.4.2. DESCRIPTION
The upper part shows a text box used to write the name of the logic that is being
edited. For example if logic number 1 is denoted as “General Trip” then the logic
function number 1 will be denoted by this text making it easy to identify it as shown in
Figure 3-61.