Section 19 A/D Converter (ADC)
Rev. 5.00 May 29, 2006 page 537 of 698
REJ09B0146-0500
Figure 19.2 shows the data flow for access to an A/D data register.
Bus
interface
TEMP
(H'40)
Lower byte of
A/D data register
(H'40)
Upper byte of
A/D data register
(H'AA)
CPU
(H'AA)
Upper byte read
Module internal data bus
Bus
interface
TEMP
(H'40)
CPU
(H'40)
Lower byte read
Module internal data bus
Lower byte of
A/D data register
(H'40)
Upper byte of
A/D data register
(H'AA)
Figure 19.2 A/D Data Register Access Operation (Reading H'AA40)
Содержание SH7706 Series
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Страница 160: ...Section 5 Cache Rev 5 00 May 29 2006 page 112 of 698 REJ09B0146 0500 ...
Страница 370: ...Section 11 Watchdog Timer WDT Rev 5 00 May 29 2006 page 322 of 698 REJ09B0146 0500 ...
Страница 532: ...Section 16 Serial Communication Interface with FIFO SCIF Rev 5 00 May 29 2006 page 484 of 698 REJ09B0146 0500 ...
Страница 554: ...Section 17 Pin Function Controller PFC Rev 5 00 May 29 2006 page 506 of 698 REJ09B0146 0500 ...
Страница 576: ...Section 18 I O Ports Rev 5 00 May 29 2006 page 528 of 698 REJ09B0146 0500 ...
Страница 614: ...Section 21 User Debugging Interface H UDI Rev 5 00 May 29 2006 page 566 of 698 REJ09B0146 0500 ...
Страница 746: ...Index Rev 5 00 May 29 2006 page 698 of 698 REJ09B0146 0500 ...
Страница 749: ...SH7706 Group Hardware Manual ...