Rev. 5.00 May 29, 2006 page xv of xlviii
Item
Page
Revision (See Manual for Details)
9.6.1 Example of
DMA Transfer between
A/D Converter and
External Memory
(Address Reload on)
Table 9.7 Values in
the DMAC after the
Fourth Transfer Ends
299
Table amended
Items
Address reload on
Address reload off
SAR_2
H'04000080
H'04000090
DAR_2
H'003FFFF0
H'003FFFF0
DMATCR_2
H'0000007C
H'0000007C
9.7 Cautions
301,
302
Description added
13. When the DMAC transfers data under conditions (1) or (2)
below, the CPU may fetch an unexpected instruction, resulting
in program runaway, or the DMA may transfer the wrong data.
(1) At wake-up from the sleep mode when operating with a
clock ratio for I
φ
:B
φ
of other than 1:1.
(2) The internal clock frequency division ratio bits (IFC[2:0]) in
the frequency control register (FRQCR) are modified.
Note that no problem occurs if the clock ratio for I
φ
:B
φ
is 1:1
after modification of the bits. Furthermore, no problem occurs if
the frequency multiplication ratio bits (STC[2:0]) are modified at
the same time as IFC[2:0].
These problems may be avoided by either of the following
measures.
• Do not use the DMAC when in sleep mode, or set the clock
ratio for I
φ
:B
φ
to 1:1 before entering sleep mode.
• Do not use the DMAC when modifying only the internal clock
frequency division ratio bits (IFC[2:0]) to produce a clock ratio
for I
φ
:B
φ
of other than 1:1.
Section 10 Clock
Pulse Generator
(CPG)
303 to
305,
309 to
312
(Before) Internal clock
→
(After) CPU clock
10.1 Feature
305
Description amended
1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, or
leaves unchanged the input clock frequency from the CKIO pin
or PLL circuit 2.
Содержание SH7706 Series
Страница 8: ...Rev 5 00 May 29 2006 page viii of xlviii ...
Страница 160: ...Section 5 Cache Rev 5 00 May 29 2006 page 112 of 698 REJ09B0146 0500 ...
Страница 370: ...Section 11 Watchdog Timer WDT Rev 5 00 May 29 2006 page 322 of 698 REJ09B0146 0500 ...
Страница 532: ...Section 16 Serial Communication Interface with FIFO SCIF Rev 5 00 May 29 2006 page 484 of 698 REJ09B0146 0500 ...
Страница 554: ...Section 17 Pin Function Controller PFC Rev 5 00 May 29 2006 page 506 of 698 REJ09B0146 0500 ...
Страница 576: ...Section 18 I O Ports Rev 5 00 May 29 2006 page 528 of 698 REJ09B0146 0500 ...
Страница 614: ...Section 21 User Debugging Interface H UDI Rev 5 00 May 29 2006 page 566 of 698 REJ09B0146 0500 ...
Страница 746: ...Index Rev 5 00 May 29 2006 page 698 of 698 REJ09B0146 0500 ...
Страница 749: ...SH7706 Group Hardware Manual ...