Rev. 5.00 May 29, 2006 page xlii of xlviii
Figure 24.9
PLL Synchronization Settling Time at the Returning from Standby Mode
(Return by IRQ/IRL Interrupt)............................................................................. 617
Figure 24.10 PLL Synchronization Settling Time when Frequency Multiplication
Rate Modified ...................................................................................................... 618
Figure 24.11 Reset Input Timing .............................................................................................. 620
Figure 24.12 Interrupt Signal Input Timing .............................................................................. 620
Figure 24.13
IRQOUT
Timing.................................................................................................. 620
Figure 24.14 Bus Release Timing ............................................................................................. 621
Figure 24.15 Pin Drive Timing at Standby ............................................................................... 621
Figure 24.16 Basic Bus Cycle (No Wait) .................................................................................. 624
Figure 24.17 Basic Bus Cycle (One Wait) ................................................................................ 625
Figure 24.18 Basic Bus Cycle (External Wait) ......................................................................... 626
Figure 24.19 Burst ROM Bus Cycle (No Wait) ........................................................................ 627
Figure 24.20 Burst ROM Bus Cycle (Two Waits) .................................................................... 628
Figure 24.21 Burst ROM Bus Cycle (External Wait) ............................................................... 629
Figure 24.22 Synchronous DRAM Read Bus Cycle (RCD
=
0, CAS Latency
=
1, TPC
=
0) .. 630
Figure 24.23 Synchronous DRAM Read Bus Cycle (RCD
=
2, CAS Latency
=
2, TPC
=
1) .. 631
Figure 24.24 Synchronous DRAM Read Bus Cycle
(Burst Read (Single Read
×
4), RCD
=
0, CAS Latency
=
1, TPC
=
1) .............. 632
Figure 24.25 Synchronous DRAM Read Bus Cycle
(Burst Read (Single Read
×
4), RCD
=
1, CAS Latency
=
3, TPC
=
0) .............. 633
Figure 24.26 Synchronous DRAM Write Bus Cycle (RCD
=
0, TPC
=
0, TRWL = 0) ........... 634
Figure 24.27 Synchronous DRAM Write Bus Cycle (RCD
=
2, TPC
=
1, TRWL = 1) ........... 635
Figure 24.28 Synchronous DRAM Write Bus Cycle
(Burst Mode (Single Write
×
4), RCD
=
0, TPC
=
1, TRWL = 0)....................... 636
Figure 24.29 Synchronous DRAM Write Bus Cycle
(Burst Mode (Single Write
×
4), RCD
=
1, TPC
=
0, TRWL = 0)....................... 637
Figure 24.30 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Same Row Address, CAS Latency = 1) ......................................... 638
Figure 24.31 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Same Row Address, CAS Latency = 2) ......................................... 639
Figure 24.32 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1).... 640
Figure 24.33 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1).... 641
Figure 24.34 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Same Row Address) ....................................................................... 642
Figure 24.35 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 0, RCD = 0) ................................. 643
Figure 24.36 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 1) ................................. 644
Содержание SH7706 Series
Страница 8: ...Rev 5 00 May 29 2006 page viii of xlviii ...
Страница 160: ...Section 5 Cache Rev 5 00 May 29 2006 page 112 of 698 REJ09B0146 0500 ...
Страница 370: ...Section 11 Watchdog Timer WDT Rev 5 00 May 29 2006 page 322 of 698 REJ09B0146 0500 ...
Страница 532: ...Section 16 Serial Communication Interface with FIFO SCIF Rev 5 00 May 29 2006 page 484 of 698 REJ09B0146 0500 ...
Страница 554: ...Section 17 Pin Function Controller PFC Rev 5 00 May 29 2006 page 506 of 698 REJ09B0146 0500 ...
Страница 576: ...Section 18 I O Ports Rev 5 00 May 29 2006 page 528 of 698 REJ09B0146 0500 ...
Страница 614: ...Section 21 User Debugging Interface H UDI Rev 5 00 May 29 2006 page 566 of 698 REJ09B0146 0500 ...
Страница 746: ...Index Rev 5 00 May 29 2006 page 698 of 698 REJ09B0146 0500 ...
Страница 749: ...SH7706 Group Hardware Manual ...