GD32W51x User Manual
876
Device all endpoints interrupt register (USBFS_DAEPINT)
Address offset: 0x0818
Reset value: 0x0000 0000
When an endpoint interrupt is triggered, USBFS sets corresponding bit in this register and
software should read this register to know which endpoint is asserting an interrupt.
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
e
se
rve
d
O
E
P
IT
B
[3
:0
]
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
e
se
rve
d
IE
P
IT
B
[3
:0
]
r
Bits
Fields
Descriptions
31:20
Reserved
Must be kept at reset value
19:16
OEPITB[3:0]
Device all OUT endpoint interrupt bits
Each bit represents an OUT endpoint:
Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3.
15:4
Reserved
Must be kept at reset value
3:0
IEPITB[3:0]
Device all IN endpoint interrupt bits
Each bit represents an IN endpoint:
Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3.
Device all endpoints interrupt enable register (USBFS_DAEPINTEN)
Address offset: 0x081C
Reset value: 0x0000 0000
This register can be used by software to enable or disable an endpoint’s interrupt. Only the
endpoint whose corresponding bit in this register is set is able to cause the endpoint interrupt
flag OEPIF or IEPIF in USBFS_GINTF register.
This register has to be accessed by word (32-bit)
Содержание GD32W515 Series
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