GigaDevice Semiconductor GD32W515 Series, Руководство пользователя

Страница: 167 / 1044

GD32W51x User Manual
167
15 PLLSEL PLL clock source selection
Set and reset by softw are to control the PLL clock source.
0: IRC16M clock selected as source clock of PLL
1: HXTAL clock selected as source clock of PLL
14:6 PLLN[8:0] The PLL VCO clock multiplication factor
Set and reset by softw are (only use w ord/half -w ord w rite) w hen the PLL is disable.
These bits used to generator PLL VCO clock (CK_PLLVCO) from PLL VCO source
clock (CK_PLLVCOSRC). The CK_PLLVCOSRC is described in PLLPSC bits in
RCU_PLL register.
Note: The frequency of CK_PLLVCO is betw een 64MHz to 400MHz
The value of PLLN must :
64≤PLLN≤511 (w hen SSCGON=0 in RCU_PLLSSCTL )
71≤PLLN≤504 (w hen SSCGON=1/SS_TY PE=0 in RCU_PLLSSCTL)
75≤PLLN≤508 (w hen SSCGON=1/SS_TY PE=1 in RCU_PLLSSCTL)
000000000: Reserved
000000001: Reserved
…
000111111: Reserved
001000000: CK_PLLVCO = CK_PLLVCOSR C x 64.
001000001: CK_PLLVCO = CK_PLLVCOSR C x 65.
…
111111110: CK_PLLVCO = CK_PLLVCOSR C x 510.
111111111: CK_PLLVCO = CK_PLLVCOSR C x 511.
5:0 PLLPSC[5:0] The PLL VCO source clock prescaler
Set and reset by softw are w hen the PLL is disable. These bits used to generate the
clock of PLL VCO source clock (CK_PLLVCOSR C). The PLL VCO source clock is
betw een 1M to 2MHz.
000000: Reserved.
000001: Reserved
000010: CK_PLLSRC / 2
000011: CK_PLLSRC / 3
…
111111: CK_PLLSRC / 63
6.5.3.
Clock configuration register 0 (RCU_CFG0)
Address offset: 0x08
Reset value: 0x0000 9400
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKOUT1SEL[1:0] CKOUT1DIV[2:0] CKOUT0DIV[2:0] Reserved CKOUT0SEL[1:0] RTCDIV[4:0]