GigaDevice Semiconductor GD32W515 Series, Руководство пользователя

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GD32W51x User Manual
202
6.5.25.
Additional clock control register (RCU_ADDCTL)
Address offset: 0x90
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLLFI2SDIV[5:0] Reserved
SDIOSEL[
1]
SDIODIV[5:0]
SDIOSEL
[0]
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPDFAUDIOSEL[1:0
]
I2SSEL[1:0]
HPDFSE
L
Reserved USBFSDIV[4:0]
USBFSS
EL
rw rw rw rw rw
Bits Fields Descriptions
31:30 Reserved Must be kept at reset value.
29:24 PLLFI2SDIV[5:0] The PLL divider factor for I2S clock
Set and reset by softw are to control the PLL clock divider factor for I2S clock.
000000: PLL clock divided by 1 for I2S clock
000001: PLL clock divided by 2 for I2S clock
…
111111: PLL clock divided by 64 for I2S clock
23 Reserved Must be kept at reset value.
22 SDIOSEL[1] Bit 1 of SDIOSEL
See bits 16 of . RCU_ADDCTL
21:17 SDIODIV[4:0] SDIO clock divider factor
This bit is set and reset by softw are.
00000: SDIODIV input source clock divided by 1
00001: SDIODIV input source clock divided by 2
…
11111: SDIODIV input source clock divided by 32
16 SDIOSEL[0] SDIO clock selection
Set and reset by softw are. This bit used to generate SDIO clock w hich select PLL
or PLLDIG clock.
00: PLL clock select as SDIO source clock
01: PLLDIG clock select as SDIO source clock
10: IRC16M selected as SDIO source clock
11: HXTAL selected as SDIO source clock
15:14 HPDFAUDIOSEL[1:0 HPDF AUDIO clock Source Selection