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Technical Documentation
VeriSens
®
v2.11.0-B4
326/429
Baumer Optronic GmbH
Radeberg, Germany
Timing diagram for SP and TE commands
The SP and TE commands can be sent at any time and are buffered. The system simultaneously sets a flag
to prevent further images from being acquired.
This means that all processes currently running are completed before a new one is triggered.
Example 1 (sequential processing)
All processes are completed up to result output 1. SP/TE then becomes effective.
1
SP / TE command
2
Trigger permitted
3
Trigger
4
Image acquisition
5
Image processing
6
Result
7
Value stored < 1 ms
Example 2 (overlapped, clocked processing)
The command comes after the second trigger → all processes up to trigger 1 and trigger 2 are completed,
SP/TE become effective after result 2.
1
SP / TE command
2
Trigger permitted
3
Trigger
4
Image acquisition
5
Image processing
6
Result
7
Value stored < 1 ms