Texas Instruments TM4C1294NCPDT, Datasheet

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15.4.1 Module Initialization ................................................................................................... 1072
15.4.2 Sample Sequencer Configuration ............................................................................... 1073
15.5
Register Map ............................................................................................................ 1073
15.6 Register Descriptions ................................................................................................. 1076
16 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 1161
16.1 Block Diagram ........................................................................................................... 1162
16.2 Signal Description ..................................................................................................... 1162
16.3 Functional Description ............................................................................................... 1164
16.3.1 Transmit/Receive Logic .............................................................................................. 1164
16.3.2 Baud-Rate Generation ............................................................................................... 1165
16.3.3 Data Transmission ..................................................................................................... 1166
16.3.4 Serial IR (SIR) ........................................................................................................... 1166
16.3.5 ISO 7816 Support ...................................................................................................... 1167
16.3.6 Modem Handshake Support ....................................................................................... 1168
16.3.7 9-Bit UART Mode ...................................................................................................... 1169
16.3.8 FIFO Operation ......................................................................................................... 1169
16.3.9 Interrupts .................................................................................................................. 1170
16.3.10 Loopback Operation .................................................................................................. 1171
16.3.11 DMA Operation ......................................................................................................... 1171
16.4
Initialization and Configuration .................................................................................... 1172
16.5 Register Map ............................................................................................................ 1173
16.6 Register Descriptions ................................................................................................. 1174
17 Quad Synchronous Serial Interface (QSSI) ..................................................... 1226
17.1 Block Diagram ........................................................................................................... 1226
17.2 Signal Description ..................................................................................................... 1227
17.3 Functional Description ............................................................................................... 1228
17.3.1 Bit Rate Generation ................................................................................................... 1229
17.3.2 FIFO Operation ......................................................................................................... 1229
17.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 1230
17.3.4 SSInFSS Function ..................................................................................................... 1231
17.3.5 High Speed Clock Operation ...................................................................................... 1232
17.3.6 Interrupts .................................................................................................................. 1232
17.3.7 Frame Formats ......................................................................................................... 1233
17.3.8 DMA Operation ......................................................................................................... 1240
17.4
Initialization and Configuration .................................................................................... 1240
17.4.1 Enhanced Mode Configuration ................................................................................... 1242
17.5
Register Map ............................................................................................................ 1243
17.6 Register Descriptions ................................................................................................. 1244
18 Inter-Integrated Circuit (I
2
C) Interface .............................................................. 1275
18.1 Block Diagram ........................................................................................................... 1276
18.2 Signal Description ..................................................................................................... 1277
18.3 Functional Description ............................................................................................... 1278
18.3.1 I
2
C Bus Functional Overview ...................................................................................... 1278
18.3.2 Available Speed Modes ............................................................................................. 1284
18.3.3 Interrupts .................................................................................................................. 1286
18.3.4 Loopback Operation .................................................................................................. 1287
18.3.5 FIFO and µDMA Operation ........................................................................................ 1287
18.3.6 Command Sequence Flow Charts .............................................................................. 1289
June 18, 2014 8
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