Texas Instruments TM4C1294NCPDT, Datasheet

Page: 155 / 1890

Register 8: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
Register 9: Interrupt 32-63 Clear Enable (DIS1), offset 0x184
Register 10: Interrupt 64-95 Clear Enable (DIS2), offset 0x188
Register 11: Interrupt 96-113 Clear Enable (DIS3), offset 0x18C
Note: This register can only be accessed from privileged mode.
The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds
to Interrupt 31. Bit 0 of DIS1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of
DIS2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of DIS3 corresponds to
Interrupt 96; .
See Table 2-9 on page 116 for interrupt assignments.
Interrupt 0-31 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type RW, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INT
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Interrupt Disable
Description Value
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding
INT[n]
bit in the EN0
register, disabling interrupt [n].
1
0x0000.0000 RW INT 31:0
155 June 18, 2014
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