Texas Instruments TM4C1294NCPDT, Datasheet

Page: 721 / 1890

Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028
Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit
enables the corresponding µDMA channel. Reading the register returns the enable status of the
channels. If a channel is enabled but the request mask is set (
DMAREQMASKSET ), then the
channel can be used for software-initiated transfers.
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
Type RW, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SET[n]
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SET[n]
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Channel [n] Enable Set
Description Value
µDMA Channel [n] is disabled. 0
µDMA Channel [n] is enabled. 1
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding
CLR[n]
bit in the DMAENACLR register or when the
end of a µDMA transfer occurs.
0x0000.0000 RW SET[n] 31:0
721 June 18, 2014
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