Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004
The
SYSEXCIM
register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
System Exception Interrupt Mask (SYSEXCIM)
Base 0x400F.9000
Offset 0x004
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FPIDCIM
FPDZCIM
FPIOCIM
FPUFCIM
FPOFCIM
FPIXCIM
reserved
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00
RW
reserved
31:6
Floating-Point Inexact Exception Interrupt Mask
Description
Value
The
FPIXCRIS
interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
FPISCRIS
bit in the
SYSEXCRIS
register is set.
1
0
RW
FPIXCIM
5
Floating-Point Overflow Exception Interrupt Mask
Description
Value
The
FPOFCIS
interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
FPOFCRIS
bit in the
SYSEXCRIS
register is set.
1
0
RW
FPOFCIM
4
Floating-Point Underflow Exception Interrupt Mask
Description
Value
The
FPUFCRIS
interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
FPUFCRIS
bit in the
SYSEXCRIS
register is set.
1
0
RW
FPUFCIM
3
June 18, 2014
526
Texas Instruments-Production Data
Processor Support and Exception Module
