■ PROT = 0x2
– Without password: Readable but not writable.
– With password: Readable only when unlocked, not writable under any conditions.
Additionally, access protection may be applied based on the processor mode. This configuration
allows for supervisor-only access or supervisor and user access, which is the default. Supervisor-only
access mode also prevents access by the µDMA and Debugger.
Additionally, the master block may be used to control access protection for the protection mechanism
itself. If access control for block 0 is for supervisor only, then the whole module may only be accessed
in supervisor mode.
Hidden Blocks
Hiding provides a temporary form of protection. Every block except block 0 can be hidden, which
prevents all accesses until the next reset.
This mechanism can allow a boot or initialization routine to access some data which is then made
inaccessible to all further accesses. Because boot and initialization routines control the capabilities
of the application, hidden blocks provide a powerful isolation of the data when debug is disabled.
A typical use model would be to have the initialization code store passwords, keys, and/or hashes
to use for verification of the rest of the application. Once performed, the block is then hidden and
made inaccessible until the next reset which then re-enters the initialization code.
Power and Reset Safety
Once the
EEDONE
register indicates that a location has been successfully written, the data is
retained until that location is written again. There is no power or reset race after the
EEDONE
register
indicates a write has completed.
Interrupt Control
The EEPROM module allows for an interrupt when a write completes to prevent the use of polling.
The interrupt can be used to drive an application ISR which can then write more words or verify
completion. The interrupt mechanism is used any time the
EEDONE
register goes from working to
done, whether because of an error or the successful completion of a program or erase operation.
This interrupt mechanism works for data writes, writes to password and protection registers, and
mass erase using the
EEPROM Debug Mass Erase (EEDGBME)
register. The EEPROM interrupt
is signaled to the core using the Flash memory interrupt vector. Software can determine that the
source of the interrupt was the EEPROM by examining bit 2 of the
Flash Controller Masked
Interrupt Status and Clear (FCMISC)
register.
Theory of Operation
The EEPROM operates using a traditional bank model which implements EEPROM-type cells, but
uses sector erase. Additionally, words are replicated in the blocks to allow 500K+ erase cycles when
needed, which means that each word has a latest version. As a result, a write creates a new version
of the word in a new location, making the previous value obsolete. When a block runs out of room
to store the latest version of a word, a copy buffer is used. The copy buffer copies the latest words
of each block. The original block is then erased. Finally, the copy buffer contents are copied back
to the block.
The EEPROM module includes functionality to prevent data corruption due to power-loss or a
brown-out event during programming or erase operations. These conditions prevent corruption of
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