Texas Instruments TM4C1294NCPDT, Datasheet

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Register 131: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode
Clock Gating Control (DCGCUART), offset 0x818
The DCGCUART register provides software the capability to enable and disable the UART modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.
Important: This register should be used to control the clocking for the UART modules.
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART)
Base 0x400F.E000
Offset 0x818
Type RW, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 reserved
RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0 RO reserved 31:8
UART Module 7 Deep-Sleep Mode Clock Gating Control
Description Value
UART module 7 is disabled in deep-sleep mode. 0
Enable and provide a clock to UART module 7 in deep-sleep
mode. 1
0 RW D7 7
UART Module 6 Deep-Sleep Mode Clock Gating Control
Description Value
UART module 6 is disabled in deep-sleep mode. 0
Enable and provide a clock to UART module 6 in deep-sleep
mode. 1
0 RW D6 6
UART Module 5 Deep-Sleep Mode Clock Gating Control
Description Value
UART module 5 is disabled in deep-sleep mode. 0
Enable and provide a clock to UART module 5 in deep-sleep
mode. 1
0 RW D5 5
June 18, 2014 436
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