until the specified length is completed. The Ethernet controller can be programmed to interrupt the
CPU in situations such as Frame Transmit and Receive transfer completion, and other normal/error
conditions.
The integrated Ethernet DMA communicates through two data structures:
■ Control and Status registers
■ Descriptor lists and data buffers.
The DMA writes data frames received by the MAC to the receive buffer in system memory and
transfers data frames for transmission from system memory to the MAC. Descriptors that reside in
the system memory act as pointers to these buffers.
There are two descriptor lists: one for reception and one for transmission. The base address of each
list is written into the
Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR)
register
at offset 0xC0C and the
Ethernet Mac Transmit Descriptor List Address (EMACTXDLADDR)
register at offset 0xC10, respectively.
The descriptor structure can contain up to 8 words (32 bytes). These are described in more detail
in “Enhanced and Alternate Descriptors” on page 1413. A descriptor list is forward linked (either
implicitly or explicitly). The last descriptor may point back to the first entry to create a ring structure.
Explicit chaining of descriptors is accomplished by enabling second address chaining in both the
Receive and Transmit descriptors (RDES0[14] and TDES0[20]). The descriptor lists reside in the
SRAM memory address space. Each descriptor can point to a maximum of two buffers. This enables
two buffers to be used at different physical addresses rather than contiguous buffers in memory.
The data buffer also resides in the physical memory space and consists of an entire frame or part
of a frame, but cannot exceed a single frame. Buffers contain only data and buffer status is maintained
in the descriptor. Data chaining refers to frames that span multiple data buffers. However, a single
descriptor cannot span multiple frames. The DMA skips to the next frame buffer when the
end-of-frame is detected. Data chaining can be enabled or disabled through the descriptors.
Note:
The EMAC DMA Controller only has access to internal system SRAM memory.
20.3.2.1
Burst Access
The DMA attempts to execute fixed length Burst transfers if the
FB
bit is set in the
EMACDMABUSMOD
register. The maximum burst length is indicated and limited by the
PBL
field
in the
EMACDMABUSMOD
register. The Receive and Transmit descriptors are always accessed
in the maximum possible (limited by
PBL
) burst-size for the bytes to be read.
The TX DMA initiates a transfer only when there is sufficient space in the FIFO to accommodate
the configured burst or remaining bytes of the end of a frame. When the DMA is configured for
fixed-length burst, it transfers data using the best combination of fixed burst sizes of 4, 8, or 16 and
single transactions. Otherwise when the
FB
bit is clear in the
EMACDMABUSMOD
register, the
DMA transfers data as a continuous undefined burst and single transactions.
The RX DMA initiates a data transfer only when sufficient data to accommodate the configured burst
is available in RX FIFO or when the end-of-frame (when it is less than the configured burst length)
is detected in the RX FIFO. The DMA indicates the start address and the number of transfers required
to the system. When the
FB
bit is set in the
EMACDMABUSMOD
register, then it transfers data
using the best combination of fixed burst sizes of 4, 8, or 16 and single transactions. If the end-of
frame is reached before the fixed-burst ends, then dummy transfers are performed in order to
complete the fixed-burst. Otherwise, if the
FB
bit is clear, the DMA transfers data using INCR
(undefined length) and SINGLE transactions. When the DMA is configured for address-aligned
transfers, both DMA engines ensure that the first burst transfer on the system bus is less than or
1411
June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
