Register 24: DMA Channel Map Select 2 (DMACHMAP2), offset 0x518
Each 4-bit field of the
DMACHMAP2
register configures the μDMA channel assignment as specified
Note:
To support legacy software which uses the
DMA Channel Assignment (DMACHASGN)
register, a value of 0x0 is equivalent to a
DMACHASGN
bit being clear, and a value of 0x1
is equivalent to a
DMACHASGN
bit being set.
DMA Channel Map Select 2 (DMACHMAP2)
Base 0x400F.F000
Offset 0x518
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CH20SEL
CH21SEL
CH22SEL
CH23SEL
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CH16SEL
CH17SEL
CH18SEL
CH19SEL
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
μDMA Channel 23 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00
RW
CH23SEL
31:28
μDMA Channel 22 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00
RW
CH22SEL
27:24
μDMA Channel 21 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00
RW
CH21SEL
23:20
μDMA Channel 20 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00
RW
CH20SEL
19:16
μDMA Channel 19 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00
RW
CH19SEL
15:12
μDMA Channel 18 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00
RW
CH18SEL
11:8
μDMA Channel 17 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00
RW
CH17SEL
7:4
μDMA Channel 16 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00
RW
CH16SEL
3:0
731
June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller