■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the
location, the
RXRIS
bit is set. The receive interrupt is cleared by performing a single read of the
receive FIFO, or by clearing the interrupt by writing a 1 to the
RXIC
bit.
The transmit interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger
level, the
TXRIS
bit is set. The transmit interrupt is based on a transition through level, therefore
the FIFO must be written past the programmed trigger level otherwise no further transmit interrupts
will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the
TXIC
bit.
■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the
TXRIS
bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the
TXIC
bit.
16.3.10
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work by setting
the
LBE
bit in the
UARTCTL
register (see page 1188). In loopback mode, data transmitted on the
UnTx
output is received on the
UnRx
input. Note that the
LBE
bit should be set before the UART is
enabled.
16.3.11
DMA Operation
The UART provides an interface to the μDMA controller with separate channels for transmit and
receive. The DMA operation of the UART is enabled through the
UART DMA Control
(UARTDMACTL)
register. When DMA operation is enabled, the UART asserts a DMA request on
the receive or transmit channel when the associated FIFO can transfer data. For the receive channel,
a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer
request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger
level configured in the
UARTIFLS
register. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The
single and burst DMA transfer requests are handled automatically by the μDMA controller depending
on how the DMA channel is configured.
To enable DMA operation for the receive channel, set the
RXDMAE
bit of the
DMA Control
(UARTDMACTL)
register. To enable DMA operation for the transmit channel, set the
TXDMAE
bit
of the
UARTDMACTL
register. The UART can also be configured to stop using DMA for the receive
channel if a receive error occurs. If the
DMAERR
bit of the
UARTDMACR
register is set and a receive
error occurs, the DMA receive requests are automatically disabled. This error condition can be
cleared by clearing the appropriate UART error interrupt.
When the µDMA is finished transferring data to the TX FIFO or from the RX FIFO, a dma_done
signal is sent to the UART to indicate completion. The dma_done status is indicated through the
DMATXRIS
and
DMARXIS
bits of the
UARTRIS
register. An interrupt can be generated from these
status bits by setting the
DMATXIM
and/or
DMARXIM
bits in the
UARTIM
register.
Note:
The
DMATXRIS
bit can be used to indicate the µDMA's completion of data transfer to the
TX FIFO. To indicate transfer completion from the UART's serializer, the end-of-transmission
bit (
EOT
bit) should be enabled in the
UARTCTL
register. An interrupt can be generated on
an end-of-transmission completion by setting the
EOTIM
bit of the
UARTIM
register.
See “Micro Direct Memory Access (μDMA)” on page 678 for more details about programming the
μDMA controller.
1171
June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
