bytes specified in the
I2CMBLEN
register has been transferred to the FIFO (and the
I2CMBCOUNT
register reaches 0x0). At this point, no further requests are generated until the next BURST command
is issued. If the µDMA is disabled, FIFOs will be serviced based on the interrupts active in the Master
interrupt status registers, the FIFO trigger values shown in the
I2CFIFOSTATUS
register and
completion of a BURST transfer.
When the Master module is receiving FIFO data, the Rx FIFO is initially empty and no requests are
asserted. If data is read from the slave and placed into the Rx FIFO, the
dma_sreq
signal to the
µDMA is asserted to indicate there is data to be transferred. If the Rx FIFO contains at least 4 bytes,
the
dma_req
signal is also asserted. The µDMA will continue to transfer data out of the Rx FIFO
until it has reached the amount of bytes programmed in the
I2CMBLEN
register.
Note:
The
TXFEIM
interrupt mask bit in the
I2CMIMR
register should be clear (masking the
TXFE
interrupt) when the master is performing an RX Burst from the RXFIFO and should be
unmasked before starting a TX FIFO transfers.
18.3.5.2
Slave Module
The slave module also has the capability to use the µDMA in Rx and Tx FIFO data transfers. If the
Tx FIFO is assigned to the slave module and the
TXFIFO
bit is set in the
I2CSCSR
register, the
slave module will generate a single µDMA request,
dma_sreq
, if the master module requests the
next byte transfer. If the FIFO fill level is less than the trigger level, a µDMA multiple transfer request,
dma_req
, will be asserted to continue data transfers from the µDMA.
If the Rx FIFO is assigned to the slave module and the
RXFIFO
bit is set in the
I2CSCSR
register,
then the slave module will generate a signal µDMA request,
dma_sreq
, if there is any data to be
transferred. The
dma_req
signal will be asserted when the Rx FIFO has more data than the trigger
level programmed by the
RXTRIG
bit in the
I2CFIFOCTL
register.
Note:
Best practice recommends that an application should not switch between the
I2CSDR
register and TX FIFO or vice versa for successive transactions.
18.3.6
Command Sequence Flow Charts
This section details the steps required to perform the various I
2
C transfer types in both master and
slave mode. Refer to Table 18-5 on page 1308 for further sequence information.
18.3.6.1
I
2
C Master Command Sequences
The figures that follow show the command sequences available for the I
2
C master.
1289
June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
