Texas Instruments TM4C1294NCPDT, Datasheet

Page: 1839 / 1890

Table 27-23. Main Oscillator Input Characteristics (continued)
Unit Max Nom Min Parameter Name Parameter
pF - 0.5 - PCB stray shunt capacitance
c
C
PCB
pF 4 - - Total shunt capacitance
c
C
SHUNT
Ω 300 - - Crystal effective series resistance, 4 MHz
de
ESR
Ω 200 - - Crystal effective series resistance, 6 MHz
de
Ω 130 - - Crystal effective series resistance, 8 MHz
de
Ω 120 - - Crystal effective series resistance, 12 MHz
de
Ω 100 - - Crystal effective series resistance, 16 MHz
de
Ω 50 - - Crystal effective series resistance, 25 MHz
de
mW - OSC
PWR
- Oscillator output drive level
f
DL
ms 18 - - Oscillator startup time, when using a crystal
g
T
START
V V
DD
- 0.65 * V
DD
CMOS input high level, when using an external
oscillator V
IH
V 0.35 * V
DD
- GND CMOS input low level, when using an external
oscillator V
IL
mV - - 150 CMOS input buffer hysteresis, when using an external
oscillator V
HYS
% 55 - 45 External clock reference duty cycle DC
OSC_EXT
a. Refer to Table 27-50 on page 1871 and Table 27-51 on page 1871 for additional Ethernet crystal requirements.
b. 5 MHz is the minimum when using the PLL.
c. See information below table.
d. Crystal ESR specified by crystal manufacturer.
e. Crystal vendors can be contacted to confirm these specifications are met for a specific crystal part number if the vendors
generic crystal datasheet show limits outside of these specifications.
f. OSC
PWR
= (2 * pi * F
P
* C
L
* 2.5)
2
* ESR / 2. An estimation of the typical power delivered to the crystal is based on the C
L
,
F
P
and ESR parameters of the crystal in the circuit as calculated by the OSC
PWR
equation. Ensure that the value
calculated for OSC
PWR
does not exceed the crystal's drive-level maximum.
g. Oscillator startup time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation
such that the internal clock is valid.
The load capacitors added on the board, C
1
and C
2
, should be chosen such that the following
equation is satisfied (see Table 27-23 on page 1838 for typical values and Table 27-24 on page 1840
for detailed crystal parameter information).
■ C
L
= load capacitance specified by crystal manufacturer
■ C
L
= (C
1
*C
2
)/(C
1
+C
2
) + C
SHUNT
■ C
SHUNT
= C
0
+ C
PKG
+ C
PCB
(total shunt capacitance seen across OSC0, OSC1 crystal inputs)
■ C
PKG
, C
PCB
= the mutual caps as measured across the OSC0,OSC1 pins excluding the crystal.
■ C
0
= Shunt capacitance of crystal specified by the crystal manufacturer
Table 27-24 on page 1840 lists part numbers of crystals that have been simulated and confirmed to
operate within the specifications in Table 27-23 on page 1838. Other crystals that have nearly identical
crystal parameters can be expected to work as well.
In the table below, the crystal parameters labeled C0, C1 and L1 are values that are obtained from
the crystal manufacturer. These numbers are usually a result of testing a relevant batch of crystals
1839 June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller