Texas Instruments TM4C1294NCPDT, Datasheet

Page: 625 / 1890

Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations for flash space that is not user configurable (that is,
FMPREn ,
FMPPEn , USER_REGn , BOOTCFG ), this register contains a 16 KB-aligned CPU byte address and
specifies which block is erased. Note that the alignment requirements must be met by software or
the results of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type RW, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
OFFSET reserved
RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OFFSET
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0x0 RO reserved 31:20
Address Offset
Address offset in Flash memory where operation is performed, except
for non-volatile registers (see “Non-Volatile Register Programming--
Flash Memory Resident Registers” on page 613 for details on values for
this field).
0x0 RW OFFSET 19:0
625 June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller