2.
Address and data are separate with 8 or 16 bits of data and up to 20 bits of address (1 MB).
This scheme is used by more modern 8051 devices, as well as some PIC and ATmega parts.
This mode is generally used with SRAMs in continuous read modes, many EEPROMs, and
many NOR Flash memory devices. Note that there is no hardware command write support for
Flash memory devices; this mode should only be used for Flash memory devices programmed
at manufacturing time. If a Flash memory device must be written and does not support a direct
programming model, the command mechanism must be performed in software. The CSn
configuration should be used in this mode. The CSn signal indicates when the address and
data phases of a read or write access is occurring. The CSn configuration is controlled by
configuring the
CSCFG
field to be 0x1 and the
CSCFGEXT
bit to be 0 in the
EPIHBnCFG2
register.
3.
Continuous read mode where address and data are separate. This read sub-mode is used by
some SRAMs and can read more quickly by only changing the address (and not using RDn/OEn
strobing). In this sub-mode, reads are performed by keeping the read mode selected (output
enable is asserted) and then changing the address pins. The data pins are changed by the
SRAM after the address pins change. For example, to read data from address 0x100 and then
0x101, the EPI controller asserts the output-enable signal and then configures the address pins
to 0x100; the EPI controller then captures what is on the data pins and increments A0 to 1 (so
the address is now 0x101); the EPI controller then captures what is on the data pins. Note that
this mode consumes higher power because the SRAM must continuously drive the data pins.
This mode is not practical in HB16 mode for normal SRAMs because there are generally not
enough address bits available. Writes are not permitted in this mode.
4.
FIFO mode uses 8 or 16 bits of data, removes ALE and address pins and optionally adds external
XFIFO FULL/EMPTY flag inputs. This scheme is used by many devices, such as radios,
communication devices (including USB2 devices), and some FPGA configurations (FIFO through
block RAM). This sub-mode provides the data side of the normal Host-Bus interface, but is
paced by the FIFO control signals. It is important to consider that the XFIFO FULL/EMPTY
control signals may stall the interface and could have an impact on blocking read latency from
the processor or μDMA. Note that the EPI FIFO can only be used in asynchronous mode.
For the three modes above (1, 2, 4) that the Host-Bus 16 mode supports, byte select signals can
be optionally implemented by setting the
BSEL
bit in the
EPIHB16CFG
register.
Note:
Byte accesses should not be attempted if the
BSEL
bit has not been enabled in Host-Bus
16 Mode.
See “External Peripheral Interface (EPI)” on page 1853 for timing details for the Host-Bus mode.
11.4.3.6
Bus Operation
Bus operation is the same in Host-Bus 8 and Host-Bus 16 modes and is asynchronous. Timing
diagrams show both ALE and CSn operation. The optional HB16 byte select signals have the same
timing as the address signals. If wait states are required in the bus access, they can be inserted
during the data phase of the access using the
WRWS
and
RDWS
bits in the
EPIHBnCFG2
register.
Each wait state adds 2 EPI clock cycles to the duration of the WRn or RDn strobe. During idle cycles,
the address and muxed address data signals maintain the state of the last cycle.
Figure 11-12 on page 845 shows a basic Host-Bus read cycle. Figure 11-13 on page 845 shows a
basic Host-Bus write cycle. Both of these figures show address and data signals in the
non-multiplexed mode (
MODE
field ix 0x1 in the
EPIHBnCFG
register).
June 18, 2014
844
Texas Instruments-Production Data
External Peripheral Interface (EPI)
