slave after bus recovery, the actual behavior on the bus varies. If the slave resumes in a state where
it can acknowledge the master (essentially, where it was before the bus hang), it continues where
it left off. However, if the slave resumes in a reset state (or if a forced STOP by the master causes
the slave to enter the idle state), it may ignore the master's attempt to complete the burst operation
and NAK the first data byte that the master sends or requests.
Since the behavior of slaves cannot always be predicted, it is suggested that the application software
always write the
STOP
bit in the
I
2
C Master Configuration (I2CMCR)
register during the CLTO
interrupt service routine. This limits the amount of data the master attempts to send or receive upon
bus recovery to a single byte, and after the single byte is on the wire, the master issues a STOP.
An alternative solution is to have the application software reset the I
2
C peripheral before attempting
to manually recover the bus. This solution allows the I
2
C master hardware to be returned to a known
good (and idle) state before attempting to recover a stuck bus and prevents any unwanted data
from appearing on the wire.
Note:
The Master Clock Low Timeout counter counts for the entire time
SCL
is held Low
continuously. If
SCL
is deasserted at any point, the Master Clock Low Timeout Counter is
reloaded with the value in the
I2CMCLKOCNT
register and begins counting down from this
value.
18.3.1.7
Dual Address
The I
2
C interface supports dual address capability for the slave. The additional programmable
address is provided and can be matched if enabled. In legacy mode with dual address disabled,
the I
2
C slave provides an ACK on the bus if the address matches the
OAR
field in the
I2CSOAR
register. In dual address mode, the I
2
C slave provides an ACK on the bus if either the
OAR
field in
the
I2CSOAR
register or the
OAR2
field in the
I2CSOAR2
register is matched. The enable for dual
address is programmable through the
OAR2EN
bit in the
I2CSOAR2
register and there is no disable
on the legacy address.
The
OAR2SEL
bit in the
I2CSCSR
register indicates if the address that was ACKed is the alternate
address or not. When this bit is clear, it indicates either legacy operation or no address match.
18.3.1.8
Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a 1 (High) on SDA, while another master transmits a 0 (Low),
switches off its data output stage and retires until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
If arbitration is lost when the I2C master is initiating a BURST with the TX FIFO enabled, the
application should execute the following steps to correctly handle the arbitration loss:
1.
Flush and disable the TX FIFO
2.
Clear and mask the
TXFE
interrupt by clearing the TXFEIM bit in the
I2CMIMR
register.
Once the bus is IDLE, the TXFIFO can be filled and enabled, the TXFE bit can be unmasked and
a new BURST transaction can be initiated.
June 18, 2014
1282
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
