Texas Instruments TM4C1294NCPDT, Datasheet

Page: 1096 / 1890

Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding
underflow condition is cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x018
Type RW1C, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
UV0 UV1 UV2 UV3 reserved
RW1C RW1C RW1C RW1C RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0x0000.000 RO reserved 31:4
SS3 FIFO Underflow
The valid configurations for this field are shown below. This bit is cleared
by writing a 1.
Description Value
The FIFO has not underflowed. 0
The FIFO for the Sample Sequencer has hit an underflow
condition, meaning that the FIFO is empty and a read was
requested. The problematic read does not move the FIFO
pointers, and 0s are returned. 1
0 RW1C UV3 3
SS2 FIFO Underflow
The valid configurations are the same as those for the
UV3
field. This
bit is cleared by writing a 1.
0 RW1C UV2 2
SS1 FIFO Underflow
The valid configurations are the same as those for the
UV3
field. This
bit is cleared by writing a 1.
0 RW1C UV1 1
SS0 FIFO Underflow
The valid configurations are the same as those for the
UV3
field. This
bit is cleared by writing a 1.
0 RW1C UV0 0
June 18, 2014 1096
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)