Texas Instruments TM4C1294NCPDT, Datasheet

Page: 1564 / 1890

Description Reset Type Name Bit/Field
Abnormal Interrupt Summary
Abnormal Interrupt Summary bit value is the logical OR of the following
when the corresponding interrupt bits are enabled in the
EMACDMAIM
register:
■ EMACDMARIS register, bit[1]: Transmit Process Stopped
■ EMACDMARIS register, bit[3]: Transmit Jabber Timeout
■ EMACDMARIS register, bit[4]: Receive FIFO Overflow
■ EMACDMARIS register, bit[5]: Transmit Underflow
■ EMACDMARIS register, bit[7]: Receive Buffer Unavailable
■ EMACDMARIS register, bit[8]: Receive Process Stopped
■ EMACDMARIS register, bit[9]: Receive Watchdog Timeout
■ EMACDMARIS register, bit[10]: Early Transmit Interrupt
■ EMACDMARIS register, bit[13]: Fatal Bus Error
Only unmasked bits affect the Abnormal Interrupt Summary bit.
This bit must be cleared each time a corresponding bit, which causes
AIS
to be set, is cleared.
0x0 RW1C AIS 15
Early Receive Interrupt
Description Value
No early receive event has occurred. 0
The DMA has filled the first data buffer of the packet. This bit
is cleared when software writes a 1 to this bit or if bit[6] (
RI
) of
this register is set.
1
0x0 RW1C ERI 14
Fatal Bus Error Interrupt
Description Value
No bus error has occurred. 0
A bus error has occurred, as described in the Error Bit field
(
EB
[25:23]). When this bit is set, the corresponding DMA engine
disables all of its bus accesses.
This bit is cleared by writing a 1 to it.
1
0x0 RW1C FBI 13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0x0 RO reserved 12:11
Early Transmit Interrupt
Description Value
No early transmit has occurred. 0
A frame to be transmitted has been fully transferred to the TX/RX
Controller Transmit FIFO.
This bit is cleared by writing a 1 to it.
1
0x0 RW1C ETI 10
June 18, 2014 1564
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Ethernet Controller