Texas Instruments TM4C1294NCPDT, Datasheet

Page: 570 / 1890

Register 9: Hibernation RTC Trim (HIBRTCT), offset 0x024
This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles, where N is the number of clock cycles to add or subtract every 64 seconds in RTC mode or
60 seconds in calendar mode.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the
WRC
bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the
WRC
bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits
RSTWK
,
PADIOWK
and
WC
of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the
CLK32EN
bit in the HIBCTL
register has been set may produce unexpected results.
Hibernation RTC Trim (HIBRTCT)
Base 0x400F.C000
Offset 0x024
Type RW, reset 0x0000.7FFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TRIM
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Reset
Description Reset Type Name Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0x0000 RO reserved 31:16
RTC Trim Value
This value is loaded into the RTC predivider every 64 seconds in RTC
counter mode.
In calendar mode, the value is loaded every 60 seconds.
It is used to adjust the RTC rate to account for drift and inaccuracy in
the clock source. Compensation can be adjusted by software by moving
the default value of 0x7FFF up or down. Moving the value up slows
down the RTC and moving the value down speeds up the RTC.
0x7FFF RW TRIM 15:0
June 18, 2014 570
Texas Instruments-Production Data
Hibernation Module