If the QSSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified
by the
SSInFss
master signal being driven Low. The master
SSInDAT0/SSInTX
output pad is
enabled. After an additional one-half
SSInClk
period, both master and slave data are enabled onto
their respective transmission lines. At the same time,
SSInClk
is enabled with a falling edge
transition. Data is then captured on the rising edges and propagated on the falling edges of the
SSInClk
signal.
After all bits have been transferred, in the case of a single word transmission, the
SSInFss
line is
returned to its idle high state one
SSInClk
period after the last bit has been captured.
For continuous back-to-back transmissions, the
SSInFss
pin remains in its active Low state until
the final bit of the last word has been captured and then returns to its idle state as described above.
For continuous back-to-back transfers, the
SSInFss
pin is held Low between successive data words
and termination is the same as that of the single word transfer.
17.3.8
DMA Operation
The QSSI peripheral provides an interface to the μDMA controller with separate channels for transmit
and receive. The µDMA operation of the QSSI is enabled through the
SSI DMA Control
(SSIDMACTL)
register. When µDMA operation is enabled, the QSSI asserts a µDMA request on
the receive or transmit channel when the associated FIFO can transfer data.
For the receive channel, a single transfer request is asserted whenever any data is in the receive
FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is 4 or
more items. For the transmit channel, a single transfer request is asserted whenever at least one
empty location is in the transmit FIFO. The burst request is asserted whenever the transmit FIFO
has 4 or more empty slots. The single and burst µDMA transfer requests are handled automatically
by the μDMA controller depending how the µDMA channel is configured.
To enable µDMA operation for the receive channel, the
RXDMAE
bit of the
DMA Control
(SSIDMACTL)
register should be set after configuring the µDMA. To enable µDMA operation for
the transmit channel, the
TXDMAE
bit of
SSIDMACTL
should be set after configuring the µDMA.
If the µDMA is enabled and has completed a data transfer from the Tx FIFO, the
DMATXRIS
bit is
set in the
SSIRIS
register and cannot be cleared by setting the
DMATXIC
bit in the
SSI Interrupt
Clear (SSIICR)
register. In the DMA Completion Interrupt Service Routine, software must disable
the µDMA transmit enable to the SSI by clearing the
TXDMAE
bit in the
QSSI DMA Control
(SSIDMACTL)
register and then setting the
DMATXIC
bit in the
SSIICR
register. This clears the
DMA completion interrupt. When the µDMA is needed to transmit more data, the
TXDMAE
bit must
be set (enabled) again.
If a data transfer by the µDMA from the Rx FIFO completes, the
DMARXRIS
bit is set. The
EOT
bit
in the
SSIRIS
register is also provided to indicate when the Tx FIFO is empty and the last bit has
been transmitted out of the serializer
Note:
Wait states are inserted at every byte transfer when using Bi- or Quad-SSI modes as a
master with the μDMA at SSICLK frequencies greater than 1/6 of the system clock. These
wait states are because of arbitration stall cycles from the μDMA accesses to SRAM and
increased output throughput from the SSI.
See “Micro Direct Memory Access (μDMA)” on page 678 for more details about programming the
μDMA controller.
17.4
Initialization and Configuration
To enable and initialize the QSSI, the following steps are necessary:
June 18, 2014
1240
Texas Instruments-Production Data
Quad Synchronous Serial Interface (QSSI)
