Texas Instruments TM4C1294NCPDT, Datasheet

Page: 1173 / 1890

4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Configure the UART clock source by writing to the UARTCC register.
6. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 678)
and enable the DMA option(s) in the
UARTDMACTL register.
7. Enable the UART by setting the
UARTEN
bit in the UARTCTL register.
16.5 Register Map
Table 16-3 on page 1173 lists the UART registers. The offset listed is a hexadecimal increment to the
register's address, relative to that UART's base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000
■ UART3: 0x4000.F000
■ UART4: 0x4001.0000
■ UART5: 0x4001.1000
■ UART6: 0x4001.2000
■ UART7: 0x4001.3000
The UART module clock must be enabled before the registers can be programmed (see page 388).
There must be a delay of 3 system clocks after the UART module clock is enabled before any UART
module registers are accessed.
The UART must be disabled (see the
UARTEN
bit in the UARTCTL register on page 1188) before any
of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation,
the current transaction is completed prior to the UART stopping.
Note: Registers that contain bits for modem control or status only apply to the following UARTs:
■ UART0 (modem flow control and modem status)
■ UART1 (modem flow control and modem status)
■ UART2 (modem flow control)
■ UART3 (modem flow control)
■ UART4 (modem flow control)
Table 16-3. UART Register Map
See
page
Description Reset Type Name Offset
1175 UART Data 0x0000.0000 RW UARTDR 0x000
1177 UART Receive Status/Error Clear 0x0000.0000 RW UARTRSR/UARTECR 0x004
1180 UART Flag 0x0000.0090 RO UARTFR 0x018
1183 UART IrDA Low-Power Register 0x0000.0000 RW UARTILPR 0x020
1173 June 18, 2014
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TM4C1294NCPDT Microcontroller