The cyclic values are transferred by the PCS 7 standard blocks
FbAnIn
(process value
PV
) and
FbAnTot
(Totalizer), the acyclic values are transferred by the
PiDr64
block to and from the
device.
The process tag type contains the required interconnections between the blocks mentioned
above. If a totalizer is not configured in the HW Config, please use the "SitransP PA" template,
otherwise the "SitransP PA Totalizer" template.
To instantiate the template, the
PV
inputs of the
Pcs7AnIn
block (process value PV) and the
FbAnTot
block (Totalizer) are interconnected with the corresponding input double word from
the HW Config. The
Laddr
input of the
PiDr64
block (
AcyclicData
) is configured with the
address of the process value
PV
(not interconnected!).
The connected module type is configured at the
DevType
input. At the
Feature
bits 18 and
19 it must be configured whether a totalizer is connected and which of its functions are used,
if necessary. All required information can be found in HW Config.
11.1.8
Operator control & monitoring
11.1.8.1
Views of SitrP_PA
Views of the SitrP_PA block
The SitrP_PA block has the following views:
● Standard view of SitrP_PA (Page 446)
● Alarm view (Page 34)
● Limit view of SitrP_PA (Page 450)
● Trend view (Page 36)
● Parameter view of SitrP_PA (Page 452)
● Preview of SitrP_PA (Page 454)
● Memo view (Page 35)
● Batch view (Page 33)
● Min/min/max pointer view of Sitr_P (resettable) (Page 456)
For general information on the faceplate and block icon, refer to the sections "Faceplate
structure" and "Block icon structure" in the APL online help.
SITRANS P PA
11.1 SitrP_PA
SITRANS Library for PCS 7
Function Manual, 05/2019, A5E35351976-11
445
Summary of Contents for SITRANS PCS 7
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