Before copying the templates into a project, you must first copy the standard PCS 7 blocks from
the APL into the SITRANS library because they are not supplied due to licensing reasons.
These are the driver blocks Or08, SelST16, Pcs7InDi, Pcs7AnIn, Pcs7AnOu, FbAnIn, FbAnOu
and the Intlk02 block.
SIPART PS2 PA
This template is used to connect a SIPART PS2 PA.
The driver blocks BE1/BE2, Rbk, MV, A1Act/A2Act and AModF must either be interconnected
to the corresponding I/O address or deleted if their functionality is not needed.
Optionally, the Permit, Interlock and Protect blocks can be interconnected with other blocks.
Because no configuration data can be read from the device acyclically, the following inputs of
the SIPART PS2 PA block may need to be configured to match their setting in the device:
Block parameters
Parameters on SI‐
PART PS2 PA
Meaning
Parameterization required
MV_OpScale.Low/
MV_OpScale.High
35.YA/36.YE
Manipulated varia‐
ble limit start/end
always
Bin1/Bin2
42.BIN1/43.BIN2
Function of the in‐
puts BE1/BE2
When inputs BE1/BE2 are
used
AFct
44.AFCT
Alarm function
When an alarm module is
used (inputs
A1Ac
t/
A2Act
)
A1/A2
45.A1/46.A2
Response threshold
Alarm1/Alarm2
When an alarm module is
used (inputs
A1Act
/
A2Act
)
Tim/Lim
48.TIM/49.LIM
Monitoring time/
Response threshold
for fault message
"Controller error"
When
LIM
and
TIM
are to
be displayed in the faceplate
SIPART PS2 PA
This template is used when SIPART PS2 PA is connected to the controller via a PROFIBUS
module.
The driver blocks BE1/BE2, Rbk, MV, A1Act/A2Act and AModF must be interconnected either
to the corresponding I/O address or deleted, if their functionality is not needed. The Laddr input
of the AcyclicData block is assigned the base address of the SipartPS2PA from the HW Config.
Optionally, the Permit, Interlock and Protect blocks can be interconnected with other blocks.
SIPART PS2 Profibus PA
This template is used when the SIPART PS2 PA is connected to the controller via Profibus PA.
The driver blocks CyclicData, A1Act/A2Act and AModF must be interconnected either to the
corresponding I/O address or deleted, if their functionality is not needed. The Laddr input of the
AcyclicData block is assigned the base address of the SIPART PS2 PA from the HW Config.
The IN input of the CbkBy2 block must be manually interconnected to the same address as the
CbkBy2 input of the CyclicData block which is automatically interconnected by the driver
wizard.
SIPART PS2 PA
8.1 SipPS2PA
SITRANS Library for PCS 7
Function Manual, 05/2019, A5E35351976-11
303
Summary of Contents for SITRANS PCS 7
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Page 418: ...SITRANS P 10 2 SitraPDr SITRANS Library for PCS 7 418 Function Manual 05 2019 A5E35351976 11 ...
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