Renesas H8SX/1650, Hardware Manual

Page: 464 / 692

Section 12 Watchdog Timer (WDT)
Rev.2.00 Jun. 28, 2007 Page 442 of 666
REJ09B0311-0200
12.4 Operation
12.4.1 Watchdog Timer Mode
To use the WDT in watchdog timer mode, set both the WT/
IT
and TME bits in TCSR to 1.
During watchdog timer operation, if TCNT overflows without being rewritten because of a system
crash or other error, the
WDTOVF
signal is output. This ensures that TCNT does not overflow
while the system is operating normally. Software must prevent TCNT overflows by rewriting the
TCNT value (normally H'00 is written) before overflow occurs. This
WDTOVF
signal can be used
to reset the LSI internally in watchdog timer mode.
If TCNT overflows when the RSTE bit in RSTCSR is set to 1, a signal that resets this LSI
internally is generated at the same time as the
WDTOVF
signal. If a reset caused by a signal input
to the
RES
pin occurs at the same time as a reset caused by a WDT overflow, the
RES
pin reset
has priority and the WOVF bit in RSTCSR is cleared to 0.
The
WDTOVF
signal is output for 133 states with P
φ
when RSTE = 1 in RSTCSR, and for 130
states with P
φ
when RSTE = 0 in RSTCSR. The internal reset signal is output for 519 states with
P
φ
.
When the RSTE bit
=
1, an internal reset signal is generated. As this signal resets the system clock
control register (SCKCR), the magnification power of P
φ
to the input clock becomes the initial
value. When the RSTE bit
=
0, no internal reset signal is generated. Therefore, the setting of
SCKCR is retained and the magnification power of P
φ
to the input clock does not change.
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT
overflows when the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the
entire LSI.