Renesas H8SX/1650, Hardware Manual

Page: 164 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 142 of 666
REJ09B0311-0200
6.2.11 Burst ROM Interface Control Register (BROMCR)
BROMCR specifies the burst ROM interface.
Bit
Bit Name
Initial Value
R/W
15
BSRM0
0
R/W
14
BSTS02
0
R/W
13
BSTS01
0
R/W
12
BSTS00
0
R/W
11

0
R
10

0
R
9
BSWD01
0
R/W
8
BSWD00
0
R/W
Bit
Bit Name
Initial Value
R/W
7
BSRM1
0
R/W
6
BSTS12
0
R/W
5
BSTS11
0
R/W
4
BSTS10
0
R/W
3

0
R
2

0
R
1
BSWD11
0
R/W
0
BSWD10
0
R/W
Bit Bit Name
Initial
Value R/W Description
15 BSRM0 0 R/W Area 0 Burst ROM Interface Select
Selects the area 0 bus interface. When setting this bit to
1, clear the BCSEL0 bit in SRAMCR to 0.
0: Basic bus interface or byte control SRAM interface
1: Burst ROM interface
14
13
12
BSTS02
BSTS01
BSTS00
0
0
0
R/W
R/W
R/W
Area 0 Burst Cycle Select
Specifies the number of burst cycles of area 0
000: 1 cycle
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: 6 cycles
110: 7 cycles
111: 8 cycles
11, 10

All 0 R Reserved
These are read-only bits and cannot be modified.