Section 4 Exception Handling
Rev.2.00 Jun. 28, 2007 Page 74 of 666
REJ09B0311-0200
RES
RD
HWR
,
LWR
D15 to D0
High
*
*
*
B
φ
Address bus
Vector fetch
Internal
operation
First instruction
prefetch
(1)
(2)
(4)
(6)
(3)
(5)
(1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5) = (2)(4))
(6) First instruction in the exception handling routine
Note:
*
Seven program wait cycles are inserted.
Figure 4.2 Reset Sequence
(16-Bit External Access in On-chip ROM Disabled Advanced Mode)
Summary of Contents for H8SX/1650
Page 2: ...Rev 2 00 Jun 28 2007 Page ii of xxii...
Page 106: ...Section 4 Exception Handling Rev 2 00 Jun 28 2007 Page 84 of 666 REJ09B0311 0200...
Page 142: ...Section 5 Interrupt Controller Rev 2 00 Jun 28 2007 Page 120 of 666 REJ09B0311 0200...
Page 326: ...Section 8 I O Ports Rev 2 00 Jun 28 2007 Page 304 of 666 REJ09B0311 0200...
Page 470: ...Section 12 Watchdog Timer WDT Rev 2 00 Jun 28 2007 Page 448 of 666 REJ09B0311 0200...
Page 566: ...Section 14 A D Converter Rev 2 00 Jun 28 2007 Page 544 of 666 REJ09B0311 0200...
Page 574: ...Section 16 RAM Rev 2 00 Jun 28 2007 Page 552 of 666 REJ09B0311 0200...
Page 584: ...Section 17 Clock Pulse Generator Rev 2 00 Jun 28 2007 Page 562 of 666 REJ09B0311 0200...
Page 638: ...Section 19 List of Registers Rev 2 00 Jun 28 2007 Page 616 of 666 REJ09B0311 0200...
Page 668: ...Section 20 Electrical Characteristics Rev 2 00 Jun 28 2007 Page 646 of 666 REJ09B0311 0200...
Page 676: ...Appendix Rev 2 00 Jun 28 2007 Page 654 of 666 REJ09B0311 0200...
Page 688: ...Rev 2 00 Jun 28 2007 Page 666 of 666 REJ09B0311 0200...
Page 691: ......
Page 692: ...H8SX 1650 Group Hardware Manual...
