Renesas H8SX/1650, Hardware Manual

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Section 7 Data Transfer Controller (DTC)
Rev.2.00 Jun. 28, 2007 Page 235 of 666
REJ09B0311-0200
7.5.2 Transfer Information Read Skip Function
By setting the RRS bit of DTCCR, the vector address read and transfer information read can be
skipped. The current DTC vector number is always compared with the vector number of previous
activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without
reading the vector address and transfer information. If the previous activation is a chain transfer,
the vector address read and transfer information read are always performed. Figure 7.6 shows the
transfer information read skip timing.
To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the
vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is
cleared to 0, the stored vector number is deleted, and the updated vector table and transfer
information are read at the next activation.
Clock
Vector read
Note: Transfer information read is skipped when the activation sources of (1) and (2) (vector numbers) are the same while RRS = 1.
(1) (2)
Transfer information
read
Data
transfer
Transfer information
write
Address
DTC activation
request
DTC request
Transfer information
read skip
R W
Data
transfer
Transfer information
write
R W
Figure 7.6 Transfer Information Read Skip Timing