Renesas H8SX/1650, Hardware Manual

Page: 219 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 197 of 666
REJ09B0311-0200
Figure 6.33 shows an example of the operation. In the figure, both bus cycles A and B are read
access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown
in (a), and an example of avoiding the data conflict by the
CS
assertion period extension cycle in
(b).
B
φ
Address bus
Data bus
Bus cycle A Bus cycle B
CS
AH
RD
(a) Without
CS
assertion period extension cycle (CSXTn = 0)
(b) With
CS
assertion period extension cycle (CSXTn = 1)
Data hold time is long.
Data conflict
B
φ
Address bus
Data bus
Bus cycle A Bus cycle B
CS
AH
RD
Figure 6.33 Consecutive Read Accesses to Same Area
(Address/Data Multiplexed I/O Space)