Renesas H8SX/1650, Hardware Manual

Page: 229 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 207 of 666
REJ09B0311-0200
6.11 Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters continue to operate as long as there is no external
access.
In addition, in the external bus released state, the
BREQO
signal can be driven low to output a bus
request externally.
6.11.1 Operation
In external extended mode, when the BRLE bit in BCR1 is set to 1, and the ICR bit for the
corresponding pin is set to 1, the bus can be released to the external. Driving the
BREQ
pin low
issues an external bus request to this LSI. When the
BREQ
pin is sampled, at the prescribed
timing, the
BACK
pin is driven low, and the address bus, data bus, and bus control signals are
placed in the high-impedance state, establishing the external bus released state. For details on
DDR and ICR, see section 8, I/O Ports.
In the external bus released state, the CPU and DTC can access the internal space using the
internal bus. When either the CPU or DTC attempts to access the external address space, it
temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus
master to be canceled.
In the external bus released state, when write access to SCKCR is granted to set the clock
frequency, the current setting for the clock frequency is deferred until the bus request of the
external bus master is canceled. For details of the SCKCR, see section 17, Clock Pulse Generator.
If the BREQOE bit in BCR1is set to 1, the
BREQO
pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
•
When either the CPU or DTC attempts to access the external address space
•
When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clock-stop mode
•
When write access to SCKCR is granted to set the clock frequency
If an external bus release request and external access occur simultaneously, the priority is as
follows:
(High) External bus release > External access by CPU or DTC (Low)