Renesas H8SX/1650, Hardware Manual

Page: 135 / 692

Section 5 Interrupt Controller
Rev.2.00 Jun. 28, 2007 Page 113 of 666
REJ09B0311-0200
Figure 5.6 shows a block diagram of the DTC and interrupt controller.
DTCER
Select signal
IRQ
interrupt
Interrupt controller
Clear signal
I, I2 to I0
Clear signal
DTC/CPU
select
circuit
DTC control
circuit
Priority
determination
DTC
CPU
Interrupt request clear signal
Interrupt request
DTC activation request
vector number
CPU interrupt request
vector number
On-chip
peripheral
module
Interrupt request clear signal
Interrupt request
Figure 5.6 Block Diagram of DTC and Interrupt Controller
(1)
Selection of Interrupt Sources
Each interrupt source is set for a DTC activation request or a CPU interrupt request by the DTCE
bit in DTCERA to DTCERH of the DTC.
Specifying the DISEL bit in MRB of the DTC generates an interrupt request to the CPU by
clearing the DTCE bit to 0 after the individual DTC data transfer.
Note that when the DTC performs a predetermined number of data transfers and the transfer
counter indicates 0, an interrupt request is also made to the CPU by clearing the DTCE bit to 0
after the DTC data transfer.
When the same interrupt source is set as both the DTC activation source and CPU interrupt source,
the DTC must be given priority over the CPU. If the IPSETE is set to 1, the priority is determined
according to the IPR setting. Therefore, the CPUP setting or the IPR setting corresponding to the
interrupt source must be set to lower than or equal to the DTCP setting. If the CPU is given
priority over the DTC, the DTC may not be activated, and the data transfer may not be performed.
(2)
Priority Determination
The DTC activation source is selected according to the default priority, and the selection is not
affected by its mask level or priority level. For respective priority levels, see table 7.1, Interrupt
Sources, DTC Vector Addresses, and Corresponding DTCEs.