Renesas H8SX/1650, Hardware Manual

Page: 662 / 692

Section 20 Electrical Characteristics
Rev.2.00 Jun. 28, 2007 Page 640 of 666
REJ09B0311-0200
20.3.4 Timing of On-Chip Peripheral Modules
Table 20.7 Timing of On-Chip Peripheral Modules
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
,
V
SS
= AV
SS
= 0 V, P
φ
= 8 MHz to 35 MHz,
T
a
= –20
°
C to +75
°
C (regular specifications),
T
a
= –40
°
C to +85
°
C (wide-range specifications)
Item Symbol Min. Max. Unit Test Conditions
I/O ports Output data delay time t
PWD

40 ns Figure 20.21
Input data setup time t
PRS
25

ns
Input data hold time t
PRH
25

ns
TPU Timer output delay time t
TOCD

40 ns Figure 20.22
Timer input setup time t
TICS
25

ns
Timer clock input setup time t
TCKS
25

ns Figure 20.23
Timer clock
pulse width
Single-edge
setting t
TCKWH
1.5

t
cyc
Both-edge
setting t
TCKWL
2.5

t
cyc
PPG Pulse output delay time t
POD

40 ns Figure 20.24
Timer output delay time t
TMOD

40 ns Figure 20.25 8-bit
timer
Timer reset input setup time t
TMRS
25

ns Figure 20.26
Timer clock input setup time t
TMCS
25

ns Figure 20.27
Timer clock
pulse width
Single-edge
setting t
TMCWH
1.5

t
cyc
Both-edge
setting t
TMCWL
2.5

t
cyc
WDT Overflow output delay time t
WOVD

40 ns Figure 20.28
SCI Asynchronous t
Scyc
4

t
cyc
Figure 20.29 Input clock
cycle
Clocked
synchronous 6

Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr

1.5 t
cyc
Input clock fall time t
SCKf

1.5 t
cyc