Renesas H8SX/1650, Hardware Manual

Page: 146 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 124 of 666
REJ09B0311-0200
6.2 Register Descriptions
The bus controller has the following registers.
•
Bus width control register (ABWCR)
•
Access state control register (ASTCR)
•
Wait control register A (WTCRA)
•
Wait control register B (WTCRB)
•
Read strobe timing control register (RDNCR)
• CS
assertion period control register (CSACR)
•
Idle control register (IDLCR)
•
Bus control register 1 (BCR1)
•
Bus control register 2 (BCR2)
•
Endian control register (ENDIANCR)
•
SRAM mode control register (SRAMCR)
•
Burst ROM interface control register (BROMCR)
•
Address/data multiplexed I/O control register (MPXCR)
6.2.1 Bus Width Control Register (ABWCR)
ABWCR specifies the data bus width for each area in the external address space.
Bit
Bit Name
Initial Value
R/W
15
ABWH7
1
R/W
14
ABWH6
1
R/W
13
ABWH5
1
R/W
12
ABWH4
1
R/W
11
ABWH3
1
R/W
10
ABWH2
1
R/W
9
ABWH1
1
R/W
8
ABWH0
1/0
R/W
Bit
Bit Name
Initial Value
R/W
Note: * Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF.
7
ABWL7
1
R/W
6
ABWL6
1
R/W
5
ABWL5
1
R/W
4
ABWL4
1
R/W
3
ABWL3
1
R/W
2
ABWL2
1
R/W
1
ABWL1
1
R/W
0
ABWL0
1
R/W