Renesas H8SX/1650, Hardware Manual

Page: 226 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 204 of 666
REJ09B0311-0200
(5)
Relationship between Chip Select (
CS
) Signal and Read (
RD
) Signal
Depending on the system's load conditions, the
RD
signal may lag behind the
CS
signal. An
example is shown in figure 6.38. In this case, with the setting for no idle cycle insertion (a), there
may be a period of overlap between the
RD
signal in bus cycle A and the
CS
signal in bus cycle B.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the
RD
and
CS
signals. In the initial state after reset release, idle cycle indicated in (b) is set.
Bus cycle A
Bus cycle B
B
φ
Address bus
CS
(area A)
CS
(area B)
RD
T1 T2 T3 T1 T2
Bus cycle A
Bus cycle B
T1 T2 T3 T1 Ti T2
Overlap time may occur between the
CS (area B) and RD
(a) No idle cycle inserted
(IDLS1 = 0)
(b) Idle cycle inserted
(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Figure 6.38 Relationship between Chip Select (
CS
) and Read (
RD
)