Renesas H8SX/1650, Hardware Manual

Page: 597 / 692

Section 18 Power-Down States
Rev.2.00 Jun. 28, 2007 Page 575 of 666
REJ09B0311-0200
18.6 All-Module-Clock-Stop Mode
When the ACSE bit is set to 1 and all modules controlled by MSTPCR are stopped (MSTPCRA,
MSTPCRB = H'FFFFFFFF), or all modules except for the 8-bit timer are stopped (MSTPCRA,
MSTPCRB = H'F[0 to F]FFFFFF), executing a SLEEP instruction with the SSBY bit in SBYCR
cleared to 0 will cause all modules (except for the 8-bit timer* and watchdog timer), the bus
controller, and the I/O ports to stop operating, and to make a transition to all-module-clock-stop
mode at the end of the bus cycle.
All-module-clock-stop mode is cleared by an external interrupt (NMI or
IRQ0
to
IRQ11
pins),
RES
pin input, or an internal interrupt (8-bit timer* or watchdog timer), and the CPU returns to the
normal program execution state via the exception handling state. All-module-clock-stop mode is
not cleared if interrupts are disabled, if interrupts other than NMI are masked on the CPU side, or
if the relevant interrupt is designated as a DTC activation source.
When the
STBY
pin is driven low, a transition is made to hardware standby mode.
Note: * Operation or halting of the 8-bit timer can be selected by bits MSTPA11 to MSTPA8 in
MSTPCRA.
18.7 Software Standby Mode
18.7.1 Transition to Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.
However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip
peripheral functions other than the SCI, and the states of the I/O ports, are retained. Whether the
address bus and bus control signals are placed in the high-impedance state or retain the output
state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, allowing power
consumption to be significantly reduced.
If the WDT is used as a watchdog timer, it is impossible to make a transition to software standby
mode. The WDT should be stopped before the SLEEP instruction execution.