Renesas H8SX/1650, Hardware Manual

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Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.2.00 Jun. 28, 2007 Page 374 of 666
REJ09B0311-0200
(2)
Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
After a match between TCNT and TGR, the compare match signal is not generated until the
TCNT input clock is generated.
Figure 9.32 shows output compare output timing.
P
φ
TCNT input clock
TCNT N
+
1 N
Compare match
signal
TIOC pin
TGR N
Figure 9.32 Output Compare Output Timing
(3)
Input Capture Signal Timing
Figure 9.33 shows input capture signal timing.
P
φ
TCNT
N
+
1 N
TGR
Input capture
input
Input capture
signal
N
+
2
N N
+
2
Figure 9.33 Input Capture Input Signal Timing