Section 1 Overview
Rev.2.00 Jun. 28, 2007 Page 8 of 666
REJ09B0311-0200
1.3 Block
Diagram
DTC
BSC
PPG
WDT
Port 1
Port 2
Port 3
Port 5
Port 6
Port A
Port B
Port D
Port E
Port F
Port H
Port I
H8SX
CPU
RAM
Inter
nal per
ipher
al b
us
Exter
nal b
u
s
SCI
×
4 channels
Clock pulse
generator
Inter
nal system b
u
s
TMR (unit 0)
×
2 channels
TMR (unit 1)
×
2 channels
A/D converter
D/A converter
Interrupt
controller
TPU
×
6 channels
CPU:
DTC:
BSC:
WDT:
TMR:
TPU:
PPG:
SCI:
[Legend]
Central processing unit
Data transfer controller
Bus controller
Watchdog timer
8-bit timer
16-bit timer pulse unit
Programmable pulse generator
Serial communications interface
Figure 1.2 Block Diagram
Summary of Contents for H8SX/1650
Page 2: ...Rev 2 00 Jun 28 2007 Page ii of xxii...
Page 106: ...Section 4 Exception Handling Rev 2 00 Jun 28 2007 Page 84 of 666 REJ09B0311 0200...
Page 142: ...Section 5 Interrupt Controller Rev 2 00 Jun 28 2007 Page 120 of 666 REJ09B0311 0200...
Page 326: ...Section 8 I O Ports Rev 2 00 Jun 28 2007 Page 304 of 666 REJ09B0311 0200...
Page 470: ...Section 12 Watchdog Timer WDT Rev 2 00 Jun 28 2007 Page 448 of 666 REJ09B0311 0200...
Page 566: ...Section 14 A D Converter Rev 2 00 Jun 28 2007 Page 544 of 666 REJ09B0311 0200...
Page 574: ...Section 16 RAM Rev 2 00 Jun 28 2007 Page 552 of 666 REJ09B0311 0200...
Page 584: ...Section 17 Clock Pulse Generator Rev 2 00 Jun 28 2007 Page 562 of 666 REJ09B0311 0200...
Page 638: ...Section 19 List of Registers Rev 2 00 Jun 28 2007 Page 616 of 666 REJ09B0311 0200...
Page 668: ...Section 20 Electrical Characteristics Rev 2 00 Jun 28 2007 Page 646 of 666 REJ09B0311 0200...
Page 676: ...Appendix Rev 2 00 Jun 28 2007 Page 654 of 666 REJ09B0311 0200...
Page 688: ...Rev 2 00 Jun 28 2007 Page 666 of 666 REJ09B0311 0200...
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