Renesas H8SX/1650, Hardware Manual

Page: 681 / 692

Main Revisions and Additions in this Edition
Rev.2.00 Jun. 28, 2007 Page 659 of 666
REJ09B0311-0200
Item Page Revision (See Manual for Details)
8.3.2 Port Function Control
Register 1 (PFCR1) 293,
294 Modified
2
CS5SB
0
R/W
1
CS4SA
0
R/W
0
CS4SB
0
R/W
Bit Bit Name Description
7
6
CS7SA *
CS7SB *
CS7
Output Pin Select
:
10: Specifies pin PF7 as
CS7
-C output
11: Setting prohibited
5
4
CS6SA
*
CS6SB
*
CS6
Output Pin Select
:
10: Specifies pin PF7 as
CS6
-C output
11: Specifies pin PF6 as
CS6
-D output
3
2
CS5SA *
CS5SB *
CS5
Output Pin Select
:
10: Specifies pin PF7 as
CS5
-C output
11: Specifies pin PF5 as
CS5
-D output
1
0
CS4SA *
CS4SB *
CS4
Output Pin Select
Selects the output pin for
CS4
when
CS4
output is enabled (CS4E = 1)
00: Specifies pin PB0 as
CS4
-A output
01: Setting prohibited
10: Specifies pin PF7 as
CS4
-C output
11: Setting prohibited
Note: * If multiple
CS
outputs are specified to a single
pin according to the
CSn
output pin select bits
(n = 4 to 7),
…
17.5.1 Notes on Clock Pulse
Generator 559 Deleted
4. Note that the frequency of f will be changed in the
middle of a bus cycle when setting SCKCR while
executing the external bus cycle with the write-data-
buffer function.
19.2 Register Bits 598 Modified
Register
Abbreviation Bit 25/17/9/1 Bit 24/16/8/0 Module
PFCR1
CS4SA CS4SB
I/O port