Renesas H8SX/1650, Hardware Manual

Page: 155 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 133 of 666
REJ09B0311-0200
Bus cycle
T
1
T
2
RD
B
φ
Data
RD
Data
RDNn = 0
RDNn = 1
T
3
(n = 7 to 0)
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)
6.2.5
CS
Assertion Period Control Registers (CSACR)
CSACR selects whether or not the assertion periods of the chip select signals (
CSn
) and address
signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O
interface are to be extended. Extending the assertion period of the
CSn
and address signals allows
the setup time and hold time of read strobe (
RD
) and write strobe (
LHWR
/
LLWR
) to be assured
and to make the write data setup time and hold time for the write strobe become flexible.
Bit
Bit Name
Initial Value
R/W
15
CSXH7
0
R/W
14
CSXH6
0
R/W
13
CSXH5
0
R/W
12
CSXH4
0
R/W
11
CSXH3
0
R/W
10
CSXH2
0
R/W
9
CSXH1
0
R/W
8
CSXH0
0
R/W
Bit
Bit Name
Initial Value
R/W
7
CSXT7
0
R/W
6
CSXT6
0
R/W
5
CSXT5
0
R/W
4
CSXT4
0
R/W
3
CSXT3
0
R/W
2
CSXT2
0
R/W
1
CSXT1
0
R/W
0
CSXT0
0
R/W