Renesas H8SX/1650, Hardware Manual

Page: 248 / 692

Section 7 Data Transfer Controller (DTC)
Rev.2.00 Jun. 28, 2007 Page 226 of 666
REJ09B0311-0200
7.2.8 DTC Control Register (DTCCR)
DTCCR specifies transfer information read skip.
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to clear the flag.
7

0
R/W
6

0
R/W
5

0
R/W
4
RRS
0
R/W
3
RCHNE
0
R/W
2

0
R
1

0
R
0
ERR
0
R/(W) *
Bit Bit Name
Initial
Value R/W Description
7 to 5

All 0 R/W Reserved
These bits are always read as 0. The write value should
always be 0.
4 RRS 0 R/W DTC Transfer Information Read Skip Enable
Controls the vector address read and transfer information
read. A DTC vector number is always compared with the
vector number for the previous activation. If the vector
numbers match and this bit is set to 1, the DTC data
transfer is started without reading a vector address and
transfer information. If the previous DTC activation is a
chain transfer, the vector address read and transfer
information read are always performed.
0: Transfer read skip is not performed.
1: Transfer read skip is performed when the vector
numbers match.
3 RCHNE 0 R/W Chain Transfer Enable After DTC Repeat Transfer
Enables/disables the chain transfer while transfer counter
(CRAL) is 0 in repeat transfer mode.
In repeat transfer mode, the CRAH value is written to
CRAL when CRAL is 0. Accordingly, chain transfer may
not occur when CRAL is 0. If this bit is set to 1, the chain
transfer is enabled when CRAH is written to CRAL.
0: Disables the chain transfer after repeat transfer
1: Enables the chain transfer after repeat transfer
2, 1

All 0 R Reserved
These are read-only bits and cannot be modified.