Renesas H8SX/1650, Hardware Manual

Page: 460 / 692

Section 12 Watchdog Timer (WDT)
Rev.2.00 Jun. 28, 2007 Page 438 of 666
REJ09B0311-0200
12.2 Input/Output Pin
Table 12.1 shows the WDT pin configuration.
Table 12.1 Pin Configuration
Name Symbol I/O Function
Watchdog timer overflow
WDTOVF
Output Outputs a counter overflow signal in
watchdog timer mode
12.3 Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to in a method different from normal registers. For details, see section
12.6.1, Notes on Register Access.
•
Timer counter (TCNT)
•
Timer control/status register (TCSR)
•
Reset control/status register (RSTCSR)
12.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
TCSR is cleared to 0.
Bit
Bit Name
Initial Value
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W