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Renesas H8SX/1650, Hardware Manual

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Section 6

   

Bus Controller (BSC)

 

 

 

Rev.2.00  Jun. 28, 2007  Page 205 of 666 

 

 REJ09B0311-0200 

Table 6.22  Idle Cycles in Mixed Accesses to Normal Space 

IDLS IDLSEL 

IDLCA 

IDLCB 

Previous 
Access 

Next 
Access 

2 1 0 7 

to 

0  1 0  1 0 Idle 

Cycle 

 0 

 

 

 

 

 

 Disabled 

Normal space 
read 

Normal 
space read 

 1 

 0 

0  0 

 

 

1 cycle inserted 

 

 

    

0 

1   2 

cycles 

inserted 

 

 

    

1 

0   3 

cycles 

inserted 

 

 

    

1 

1   4 

cycles 

inserted 

 

 

 

 

 

1 

 

 

0 

0 

0 cycle inserted 

 

 

    

   0 

1 

2 

cycle 

inserted 

 

 

    

   1 

0 

3 

cycles 

inserted 

 

 

    

   1 

1 

4 

cycles 

inserted 

 

 0 

 

 

 

 

 Disabled 

Normal space 
read 

Normal 
space write 

 

 1 0 

0 0 

 

 

1 cycle inserted 

 

 

    

0 

1   2 

cycles 

inserted 

 

 

    

1 

0   3 

cycles 

inserted 

 

 

    

1 

1   4 

cycles 

inserted 

 

 

 

 

 

1 

 

 

0 

0 

0 cycle inserted 

 

 

    

   0 

1 

2 

cycle 

inserted 

 

 

    

   1 

0 

3 

cycles 

inserted 

 

 

    

   1 

1 

4 

cycles 

inserted 

0 

 

 

 

 

 

 

 Disabled 

Normal space 
write 

Normal 
space read 

1 

 

 

 0 

0 

 

 

1 cycle inserted 

 

 

    

0 

1   2 

cycles 

inserted 

 

 

    

1 

0   3 

cycles 

inserted 

 

 

    

1 

1   4 

cycles 

inserted 

 

Summary of Contents for H8SX/1650

Page 1: ...ime of publication of this material is subject to change by Renesas Technology Corp without notice Please review the latest information published by Renesas Technology Corp through various means inclu...

Page 2: ...Rev 2 00 Jun 28 2007 Page ii of xxii...

Page 3: ...ty and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmi...

Page 4: ...oment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the momen...

Page 5: ...isions is a summary of major points of revision or addition for earlier versions It does not cover all revised items For details on the revised points see the actual locations in the manual The follow...

Page 6: ...e 1 Overall notation 2 Register notation Rev 0 50 10 04 page 416 of 914 14 2 2 Compare Match Control Status Register_0 _1 CMCSR_0 CMCSR_1 14 3 1 Interval Count Operation 4 3 2 Binary numbers are given...

Page 7: ...icates whether the bit or field is readable or writable or both writing to and reading from the bit or field are impossible The notation is as follows R W R W R W The bit or field is readable and writ...

Page 8: ...A Asynchronous communication interface adapter bps Bits per second CRC Cyclic redundancy check DMA Direct memory access DMAC Direct memory access controller GSM Global System for Mobile Communications...

Page 9: ...isters 24 2 5 1 General Registers 25 2 5 2 Program Counter PC 26 2 5 3 Condition Code Register CCR 26 2 5 4 Extended Control Register EXR 28 2 5 5 Vector Base Register VBR 28 2 5 6 Short Address Base...

Page 10: ...ect aa 8 55 2 8 11 Extended Memory Indirect vec 7 56 2 8 12 Effective Address Calculation 56 2 8 13 MOVA Instruction 58 2 9 Processing States 59 Section 3 MCU Operating Modes 61 3 1 Operating Mode Sel...

Page 11: ...Enable Register IER 92 5 3 5 IRQ Sense Control Registers H and L ISCRH ISCRL 94 5 3 6 IRQ Status Register ISR 98 5 3 7 Software Standby Release IRQ Enable Register SSIER 99 5 4 Interrupt Sources 100 5...

Page 12: ...face Control Register BROMCR 142 6 2 12 Address Data Multiplexed I O Control Register MPXCR 144 6 3 Bus Configuration 145 6 4 Multi Clock Function and Number of Access Cycles 146 6 5 External Bus 150...

Page 13: ...6 9 6 Address Cycle Control 194 6 9 7 Wait Control 195 6 9 8 Read Strobe RD Timing 195 6 9 9 Extension of Chip Select CS Assertion Period 196 6 10 Idle Cycle 198 6 10 1 Operation 198 6 10 2 Pin State...

Page 14: ...7 5 3 Transfer Information Writeback Skip Function 236 7 5 4 Normal Transfer Mode 236 7 5 5 Repeat Transfer Mode 237 7 5 6 Block Transfer Mode 239 7 5 7 Chain Transfer 240 7 5 8 Operation Timing 241...

Page 15: ...Port H 286 8 2 12 Port I 286 8 3 Port Function Controller 292 8 3 1 Port Function Control Register 0 PFCR0 292 8 3 2 Port Function Control Register 1 PFCR1 293 8 3 3 Port Function Control Register 2...

Page 16: ...9 2 Input Clock Restrictions 381 9 9 3 Caution on Cycle Setting 382 9 9 4 Conflict between TCNT Write and Clear Operations 382 9 9 5 Conflict between TCNT Write and Increment Operations 383 9 9 6 Conf...

Page 17: ...5 Usage Notes 410 10 5 1 Module Stop State Setting 410 10 5 2 Operation of Pulse Output Pins 410 Section 11 8 Bit Timers TMR 411 11 1 Features 411 11 2 Input Output Pins 414 11 3 Register Description...

Page 18: ...12 1 Features 437 12 2 Input Output Pin 438 12 3 Register Descriptions 438 12 3 1 Timer Counter TCNT 438 12 3 2 Timer Control Status Register TCSR 439 12 3 3 Reset Control Status Register RSTCSR 441 1...

Page 19: ...ultiprocessor Serial Data Transmission 494 13 5 2 Multiprocessor Serial Data Reception 495 13 6 Operation in Clocked Synchronous Mode 498 13 6 1 Clock 498 13 6 2 SCI Initialization Clocked Synchronous...

Page 20: ...D Control Register ADCR 531 14 4 Operation 532 14 4 1 Single Mode 532 14 4 2 Scan Mode 533 14 4 3 Input Sampling and A D Conversion Time 535 14 4 4 External Trigger Input Timing 537 14 5 Interrupt Sou...

Page 21: ...ures 563 18 2 Register Descriptions 565 18 2 1 Standby Control Register SBYCR 566 18 2 2 Module Stop Control Registers A and B MSTPCRA and MSTPCRB 569 18 2 3 Module Stop Control Register C MSTPCRC 572...

Page 22: ...87 19 1 Register Addresses Address Order 588 19 2 Register Bits 597 19 3 Register States in Each Operating Mode 607 Section 20 Electrical Characteristics 617 20 1 Absolute Maximum Ratings 617 20 2 DC...

Page 23: ...t connection to different kinds of memory The LSI of the Group also includes serial communication interfaces A D and D A converters and a multi function timer that makes motor control easy Together th...

Page 24: ...bytes available 87 basic instructions classifiable as bit arithmetic and logic instructions multiply and divide instructions bit manipulation instructions multiply and accumulate instructions and othe...

Page 25: ...of DTC activation sources Activated by interrupt sources chain transfer enabled Three transfer modes normal transfer repeat transfer block transfer Short address mode or full address mode selectable...

Page 26: ...ended data transfer modules i e the CPU runs in synchronization with the system clock I 8 to 50 MHz Internal peripheral functions run in synchronization with the peripheral module clock P 8 to 35 MHz...

Page 27: ...to multiple timer counters TCNT simultaneous clearing by compare match and input capture possible simultaneous input output for registers possible by counter synchronous operation and up to 15 phase P...

Page 28: ...art card SIM interface I O ports Eight CMOS input only pins 50 CMOS input output pins Eight large current drive pins port 3 11 pull up resistors 11 open drains Package 120 pin thin QFP package package...

Page 29: ...acity Package Remarks R5S61650CFPV 24 Kbytes PLQP0120LA A FP 120BV ROMless versions only as of August 2005 Product type no R 5 S 61650C FP Indicates the package Indicates the Pb free version Indicates...

Page 30: ...bus External bus SCI 4 channels Clock pulse generator Internal system bus TMR unit 0 2 channels TMR unit 1 2 channels A D converter D A converter Interrupt controller TPU 6 channels CPU DTC BSC WDT TM...

Page 31: ...AVcc P53 AN3 IRQ3 B AVss P54 AN4 IRQ4 B Vref P55 AN5 IRQ5 B P56 AN6 DA0 IRQ6 B P57 AN7 DA1 IRQ7 B MD1 PA0 BREQO BS A PA1 BACK RD WR PA2 BREQ WAIT PA3 LLWR LLB PA4 LHWR LUB PA5 RD PA6 AS AH BS B Vss PA...

Page 32: ...ces Operating mode control MD2 to MD0 Input Pins for setting the operating mode The signal levels on these pins must not be changed during operation System control RES Input Reset signal input pin Thi...

Page 33: ...is in progress RD WR Output Indicates the direction input or output of the data bus LHWR Output Strobe signal which indicates that the higher order byte D15 to D8 is valid in access to the basic bus...

Page 34: ...A IRQ4 B IRQ3 A IRQ3 B IRQ2 A IRQ2 B IRQ1 A IRQ1 B IRQ0 A IRQ0 B Input Maskable interrupt request signal 16 bit timer pulse unit TPU TCLKA A TCLKA B TCLKB A TCLKB B TCLKC A TCLKC B TCLKD A TCLKD B Inp...

Page 35: ...utputs TIOCA5 TIOCB5 Input output Signals for TGRA_5 and TGRB_5 These pins are used as input capture inputs output compare outputs or PWM outputs Programmable pulse generator PPG PO15 to PO0 Output Ou...

Page 36: ...t in use connect this pin to the system power supply AVSS Ground pin for the A D and D A converters Connect this pin to the system power supply 0 V Vref Reference power supply pin for the A D and D A...

Page 37: ...ters 87 basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Bit field transfer instructions Powerful bit manipulation instructions Bit condition branch in...

Page 38: ...ister divide 10 states 16 16 bit register register multiply 1 state 32 16 bit register register divide 18 states 32 32 bit register register multiply 5 states 32 32 bit register register divide 18 sta...

Page 39: ...2 2 1 Normal Mode In normal mode the exception handling vector table and stack have the same structure as in the H8 300 CPU Note This LSI does not support this mode Address Space A maximum address spa...

Page 40: ...ry indirect aa 8 and extended memory indirect vec 7 addressing modes are used in the JMP and JSR instructions An 8 bit absolute address included in the instruction code specifies a memory location Exe...

Page 41: ...Instruction Set All instructions and addressing modes can be used Only the lower 16 bits of effective addresses EA are valid and the upper eight bits are sign extended Exception Handling Vector Table...

Page 42: ...g at H 00000000 is allocated to the exception handling vector table in 32 bit units In each 32 bits the upper eight bits are ignored and one branch address is stored in the lower 24 bits The structure...

Page 43: ...Modes 2 2 4 Maximum Mode The program area in maximum mode is extended to 4 Gbytes as compared with that in advanced mode Address Space A maximum address space of 4 Gbytes can be linearly accessed Exte...

Page 44: ...uded in the instruction code specifies a memory location Execution branches to the contents of the memory location In maximum mode an operand is a 32 bit longword operand providing a 32 bit branch add...

Page 45: ...data accesses The FETCHMD bit in SYSCR selects one of the two modes For details see section 3 2 2 System Control Register SYSCR 2 4 Address Space Figure 2 8 shows a memory map of the H8SX CPU The addr...

Page 46: ...E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L General Registers and Extended Registers Control Registers Legend Stack pointer Program counter Condition code r...

Page 47: ...ed registers The R registers are divided into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum of sixte...

Page 48: ...t contains internal CPU status information including an interrupt mask I and user UI U bits and half carry H negative N zero Z overflow V and carry C flags Operations can be performed on the CCR bits...

Page 49: ...t bit 27 and cleared to 0 otherwise 4 U Undefined R W User Bit Can be written and read by software using the LDC STC ANDC ORC and XORC instructions 3 N Undefined R W Negative Flag Stores the value of...

Page 50: ...All 1 R W Reserved These bits are always read as 1 The write value should always be 1 2 1 0 I2 I1 I0 1 1 1 R W R W R W Interrupt Mask Bits These bits designate the interrupt mask level 0 to 7 2 5 5 Ve...

Page 51: ...alid the upper bits are sign extended 2 5 8 Initial Register Values Reset exception handling loads the start address from the vector table into the PC contents clears the trace bit in EXR to 0 and set...

Page 52: ...ws the data formats in general registers 7 6 5 4 3 2 1 0 Don t care 7 0 Don t care 7 6 5 4 3 2 1 0 4 3 7 0 7 0 Don t care Upper Lower LSB MSB LSB 1 bit data 1 bit data 4 bit BCD data 4 bit BCD data By...

Page 53: ...yte word and byte accesses In this case these accesses are assumed to be individual bus cycles However instructions to be fetched word and longword data to be accessed during execution of the stack ma...

Page 54: ...H 1 W L LDM STM L MOVA B W 2 Block transfer EEPMOV B 3 MOVMD B W L MOVSD B ADD ADDX SUB SUBX CMP NEG INC DEC B W L 27 Arithmetic operations DAA DAS B ADDS SUBS L MULXU DIVXU MULXS DIVXS B W MULU DIVU...

Page 55: ...RC B W L Total 87 Legend B Byte size W Word size L Longword size Notes 1 POP W Rn and PUSH W Rn are identical to MOV W SP Rn and MOV W Rn SP POP L ERn and PUSH L ERn are identical to MOV L SP ERn and...

Page 56: ...d RnL B Rn W ERn L ERn ERn ERn ERn aa 8 aa 16 aa 32 B W L S SD SD SD SD SD SD MOV B S D S D MOVFPE MOVTPE 12 B S D S D 1 POP PUSH W L S D S D 2 LDM STM L S D S D 2 Data transfer MOVA 4 B W S S S S S...

Page 57: ...C O LDMAC S Arithmetic operations STMAC D AND OR XOR B W L S SD SD SD SD SD SD Logic operations NOT B W L D D D D D D SHLL SHLR B W L 6 D D D D D D B W L 7 D SHAL SHAR B W L D D D D D D ROTL ROTR B W...

Page 58: ...an be specified as either source or destination operand S 4 4 bit immediate data can be specified as a source operand Notes 1 aa 16 is only available 2 ERn as a source operand and ERn as a destination...

Page 59: ...dressing Modes 2 Addressing Mode Classifi cation Instruction Size ERn d PC RnL B Rn W ERn L PC aa 24 aa 32 aa 8 vec 7 BRA BS BRA BC O BSR BS BSR BC O Bcc O BRA O O BRA S O JMP O O O O O BSR O JSR O O...

Page 60: ...EAd Destination operand EAs Source operand EXR Extended control register CCR Condition code register VBR Vector base register SBR Short address base register N N negative flag in CCR Z Z zero flag in...

Page 61: ...ter contents on the stack LDM L SP Rn register list Restores the data from the stack to general registers Two three or four general registers which have serial register numbers can be specified STM L...

Page 62: ...by R4 MOVMD W W Transfers a data block Transfers word data from a memory location specified by ER5 to a memory location specified by ER6 The number of word data to be transferred is specified by R4 M...

Page 63: ...subtracts the value 1 2 or 4 to or from data in a general register DAA DAS B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to the CCR to pro...

Page 64: ...CMP B W L EAd IMM EAd EAs Compares data between immediate data general registers and memory and stores CCR bits according to the result NEG B W L 0 EAd EAd Takes the two s complement arithmetic compl...

Page 65: ...EAd EAd EAs EAd Performs a logical AND operation on data between immediate data general registers and memory OR B W L EAd IMM EAd EAd EAs EAd Performs a logical OR operation on data between immediate...

Page 66: ...tion 1 bit or 2 bit rotation is possible ROTXL ROTXR B W L EAd rotate EAd Rotates the contents of a general register or a memory location with the carry flag 1 bit or 2 bit rotation is possible Table...

Page 67: ...pecified bit in the contents of a general register or a memory location and stores the result in the carry flag The bit number is specified by 3 bit immediate data BIAND B C bit No of EAd C Logically...

Page 68: ...arry flag value to a specified bit in the contents of a general register or a memory location The bit number is specified by 3 bit immediate data BSTZ B Z bit No of EAd Transfers the zero flag value t...

Page 69: ...ranches to a subroutine at a specified address Bcc Branches to a specified address if the specified condition is satisfied BRA S Branches unconditionally to a specified address after executing the nex...

Page 70: ...ers are performed between them and memory The upper eight bits are valid LDC L Rs VBR Rs SBR Transfers the general register contents to VBR or SBR B W CCR EAd EXR EAd Transfers CCR or EXR contents to...

Page 71: ...isp 4 Operation field effective address extension and condition field op cc EA disp BRA d 16 etc Figure 2 14 Instruction Formats Operation Field Indicates the function of the instruction the addressin...

Page 72: ...Table 2 12 Addressing Modes No Addressing Mode Symbol 1 Register direct Rn 2 Register indirect ERn 3 Register indirect with displacement d 2 ERn d 16 ERn d 32 ERn 4 Index register indirect with displ...

Page 73: ...6 or 32 bit displacement ERn is specified by the register field of the instruction code The displacement is included in the instruction code and the 16 bit displacement is sign extended when added to...

Page 74: ...rand value is the contents of a memory location which is pointed to by the following operation result the value 1 2 or 4 is added to the contents of an address register ERn which is specified by the r...

Page 75: ...ich is pointed to by an absolute address included in the instruction code There are 8 bit aa 8 16 bit aa 16 24 bit aa 24 and 32 bit aa 32 absolute addresses To access the data area the absolute addres...

Page 76: ...H 00FFFFFF H 00000000 to H FFFFFFFF 2 8 7 Immediate xx 8 xx 16 or xx 32 The operand value is 8 bit xx 8 16 bit xx 16 or 32 bit xx 32 data included in the instruction code This addressing mode has sho...

Page 77: ...ified bits of the contents of an address register RnL Rn or ERn specified by the register field in the instruction code is zero extended to 32 bit data and multiplied by 2 The PC content to which the...

Page 78: ...the instruction code and the value of H 80 is multiplied by 2 or 4 The address range to store a branch address is H 0100 to H 01FF in normal mode and H 000200 to H 0003FF in other modes In assembler n...

Page 79: ...ective Address EA Immediate Register direct Register indirect Register indirect with 16 bit displacement Register indirect with 32 bit displacement Index register indirect with 16 bit displacement Ind...

Page 80: ...ension Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA PC contents Sign extension PC contents Zero extension Zero extension Memory contents Memory contents Ze...

Page 81: ...ailable Exception handling state The exception handling state is a transient state that occurs when the CPU alters the normal processing flow due to activation of an exception source such as a reset t...

Page 82: ...made to the reset state when the watchdog timer overflows Note Reset state Exception handling state Request for exception handling End of exception handling Program execution state Bus released state...

Page 83: ...bled 16 bits 16 bits 5 1 0 1 On chip ROM disabled extended mode Disabled 8 bits 16 bits In this LSI advanced mode for the CPU operating mode 16 Mbytes for the address space and eight or 16 bits for th...

Page 84: ...mined by pins MD2 to MD0 15 0 R 14 1 R 13 0 R 12 1 R 11 0 R 10 MDS2 Undefined R 9 MDS1 Undefined R 8 MDS0 Undefined R Bit Bit Name Initial Value R W 7 0 R 6 1 R 5 0 R 4 1 R 3 0 R 2 Undefined R 1 Undef...

Page 85: ...alue R W Descriptions 7 6 5 4 3 2 1 0 0 1 0 1 0 Undefined Undefined Undefined R R R R R R R R Reserved These are read only bits and cannot be modified Note Determined by pins MD2 to MD0 Table 3 2 Sett...

Page 86: ...W 2 0 R W 1 DTCMD 1 R W 0 1 R W Bit Bit Name Initial Value R W Descriptions 15 14 All 1 R W Reserved These bits are always read as 1 The write value should always be 1 13 MACS 0 R W MAC Saturation Op...

Page 87: ...internal bus cycle depending on the setting of the write data buffer function 0 External bus disabled 1 External bus enabled 8 RAME 1 R W RAM Enable Enables or disables the on chip RAM This bit is in...

Page 88: ...nals However if all areas are designated as an 8 bit access space by the bus controller the bus mode switches to 8 bits and only port H functions as a data bus 3 3 2 Mode 5 The CPU operating mode is a...

Page 89: ...Functions in Each Operating Mode Advanced Mode Port Mode 4 Mode 5 PA7 P C P C PA6 PA4 P C P C Port A PA2 to PA0 P C P C PB3 to 1 P C P C Port B PB0 P C P C Port D A A Port E A A Port F PF7 to PF5 P A...

Page 90: ...area is specified as the external address space by clearing the RAME bit in SYSCR to 0 On chip RAM external address space External address space External address space External address space External...

Page 91: ...en the RES pin is low Illegal instruction Exception handling starts when an undefined code is executed Trace 1 Exception handling starts after execution of the current instruction or exception handlin...

Page 92: ...3 MCU Operating Modes Table 4 2 Exception Handling Vector Table Vector Table Address Offset 1 Exception Source Vector Number Normal Mode 2 Advanced Middle 2 Maximum 2 Modes Reset 0 H 0000 to H 0001 H...

Page 93: ...0C to H 010F IRQ4 68 H 0088 to H 0089 H 0110 to H 0113 IRQ5 69 H 008A to H 008B H 0114 to H 0117 IRQ6 70 H 008C to H 008D H 0118 to H 011B IRQ7 71 H 008E to H 008F H 011C to H 011F IRQ8 72 H 0090 to H...

Page 94: ...hen operation is in progress hold the RES pin low for at least 20 cycles The chip can also be reset by overflow of the watchdog timer For details see section 12 Watchdog Timer WDT A reset initializes...

Page 95: ...Functions after Reset Release After the reset state is released MSTPCRA and MSTPCRB are initialized to H 0FFF and H FFFF respectively and all modules except the DTC enter module stop state Consequent...

Page 96: ...prefetch 1 2 4 6 3 5 1 3 Reset exception handling vector address when reset 1 H 000000 3 H 000002 2 4 Start address contents of reset exception handling vector address 5 Start address 5 2 4 6 First in...

Page 97: ...interrupt masking by CCR Table 4 4 shows the state of CCR and EXR after execution of trace exception handling Trace mode is canceled by clearing the T bit in EXR to 0 during the trace exception handl...

Page 98: ...rs Instruction fetch Fetches instructions from access prohibited area 2 Occurs CPU Accesses stack when the stack pointer value is even address No normal Stack operation Accesses stack when the stack p...

Page 99: ...PC and program execution starts from that address Even though an address error occurs during a transition to an address error exception handling the address error is not accepted This prevents an add...

Page 100: ...Address Offsets and Interrupt Priority in section 5 Interrupt Controller 4 6 2 Interrupt Exception Handling Interrupts are controlled by the interrupt controller The interrupt controller has two inter...

Page 101: ...he stack 2 The interrupt mask bit is updated and the T bit is cleared to 0 3 An exception handling vector table address corresponding to the vector number specified in the TRAPA instruction is generat...

Page 102: ...ddress corresponding to the vector number specified in the SLEEP instruction is generated the start address of the exception service routine is loaded from the vector table to PC and program execution...

Page 103: ...l illegal instruction and slot illegal instruction is always executable in the program execution state The exception handling is as follows 1 The contents of PC CCR and EXR are saved in the stack 2 Th...

Page 104: ...ack Status after Exception Handling Figure 4 3 shows the stack after completion of exception handling CCR PC 24 bits SP EXR Reserved CCR PC 24 bits SP Advanced mode Interrupt control mode 0 Interrupt...

Page 105: ...tions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Performing stack manipulation while SP is set to an odd value leads to an address error Figure 4 4 shows an example of oper...

Page 106: ...Section 4 Exception Handling Rev 2 00 Jun 28 2007 Page 84 of 666 REJ09B0311 0200...

Page 107: ...ons CPU address error DMA address error occurred in the DTC Sleep instruction Independent vector addresses All interrupt sources are assigned independent vector addresses making it unnecessary for the...

Page 108: ...selecter CPU interrupt request CPU vector DTC vector Activation request clear signal DTC activation request I I2 to I0 CCR EXR CPU DTC INTCR CPUPCR ISCR IER ISR Interrupt control register CPU priorit...

Page 109: ...IRQ11 to IRQ0 Input Maskable External Interrupts Rising falling or both edges or level sensing can be selected 5 3 Register Descriptions The interrupt controller has the following registers Interrupt...

Page 110: ...5 4 INTM1 INTM0 0 0 R W R W Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller 00 Interrupt control mode 0 Interrupts are contro...

Page 111: ...W CPU Priority Control Enable Controls the CPU priority control function Setting this bit to 1 enables the CPU priority control 0 CPU always has the lowest priority 1 CPU priority control enabled 6 5...

Page 112: ...highest Note When the IPSETE bit is set to 1 the CPU priority is automatically updated so these bits cannot be modified 5 3 3 Interrupt Priority Registers A to C E to H K and L IPRA to IPRC IPRE to IP...

Page 113: ...010 Priority level 2 011 Priority level 3 100 Priority level 4 101 Priority level 5 110 Priority level 6 111 Priority level 7 highest 11 0 R Reserved This is a read only bit and cannot be modified 10...

Page 114: ...not be modified 2 1 0 IPR2 IPR1 IPR0 1 1 1 R W R W R W Sets the priority level of the corresponding interrupt source 000 Priority level 0 lowest 001 Priority level 1 010 Priority level 2 011 Priority...

Page 115: ...interrupt request is enabled when this bit is 1 7 IRQ7E 0 R W IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1 6 IRQ6E 0 R W IRQ6 Enable The IRQ6 interrupt request is enabled when...

Page 116: ...ing the setting of ISCR should be changed while the IRQn interrupt is disabled and then the IRQnF in ISR should be cleared to 0 ISCRH Bit Bit Name Initial Value R W Bit Bit Name Initial Value R W 15 0...

Page 117: ...uest generated by low level of IRQ10 01 Interrupt request generated at falling edge of IRQ10 10 Interrupt request generated at rising edge of IRQ10 11 Interrupt request generated at both falling and r...

Page 118: ...equest generated at falling edge of IRQ6 10 Interrupt request generated at rising edge of IRQ6 11 Interrupt request generated at both falling and rising edges of IRQ6 11 10 IRQ5SR IRQ5SF 0 0 R W R W I...

Page 119: ...st generated at falling edge of IRQ2 10 Interrupt request generated at rising edge of IRQ2 11 Interrupt request generated at both falling and rising edges of IRQ2 3 2 IRQ1SR IRQ1SF 0 0 R W R W IRQ1 Se...

Page 120: ...W Bit Bit Name Initial Value R W Description 15 to 12 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 11 10 9 8 7 6 5 4 3 2 1 0 IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IR...

Page 121: ...0 R W 5 SSI5 0 R W 4 SSI4 0 R W 3 SSI3 0 R W 2 SSI2 0 R W 1 SSI1 0 R W 0 SSI0 0 R W Bit Bit Name Initial Value R W Description 15 to 12 All 0 R W Reserved These bits are always read as 0 The write val...

Page 122: ...ERR bit in DTCCR to 1 2 IRQn Interrupts An IRQn interrupt is requested by a signal input on pins IRQ11 to IRQ0 IRQn n 11 to 0 have the following features Using ISCR it is possible to select whether an...

Page 123: ...dling routine and clear the IRQnF to 0 Interrupts may not be executed when the corresponding input signal IRQn is set to high before the interrupt handling begins 5 4 2 Internal Interrupts The sources...

Page 124: ...y are fixed Table 5 2 Interrupt Sources Vector Address Offsets and Interrupt Priority Classification Interrupt Source Vector Number Vector Address Offset IPR Priority DTC Activation External pin NMI 7...

Page 125: ...TGI0B 89 H 0164 O TGI0C 90 H 0168 O TGI0D 91 H 016C O TCI0V 92 H 0170 TPU_1 TGI1A 93 H 0174 IPRF2 to IPRF0 O TGI1B 94 H 0178 O TCI1V 95 H 017C TCI1U 96 H 0180 TPU_2 TGI2A 97 H 0184 IPRG14 to IPRG12 O...

Page 126: ...2 O CMI0B 117 H 01D4 O OV0I 118 H 01D8 TMR_1 CMI1A 119 H 01DC IPRH10 to IPRH8 O CMI1B 120 H 01E0 O OV1I 121 H 01E4 TMR_2 CMI2A 122 H 01E8 IPRH6 to IPRH4 O CMI2B 123 H 01EC O OV2I 124 H 01F0 TMR_3 CMI3...

Page 127: ...024C SCI_1 ERI1 148 H 0250 IPRK2 to IPRK0 RXI1 149 H 0254 O TXI1 150 H 0258 O TEI1 151 H 025C SCI_2 ERI2 152 H 0260 IPRL14 to IPRL12 RXI2 153 H 0264 O TXI2 154 H 0268 O TEI2 155 H 026C Reserved for sy...

Page 128: ...interrupt requests except for NMI are masked by the I bit in CCR of the CPU Figure 5 3 shows a flowchart of the interrupt acceptance operation in this case 1 If an interrupt request occurs when the co...

Page 129: ...t handling routine at the address indicated by the contents of the vector address in the vector table Program execution state Interrupt generated NMI IRQ0 IRQ1 SSTXI2 I 0 Save PC and CCR I 1 Read vect...

Page 130: ...able 5 2 3 Next the priority of the selected interrupt request is compared with the interrupt mask level set in EXR When the interrupt request does not have priority over the mask level set it is held...

Page 131: ...Mask level 5 or below Level 7 interrupt Mask level 6 or below Save PC CCR and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Pending Level 1 interrupt...

Page 132: ...tion prefetch in interrupt handling routine Internal operation Vector fetch Stack Internal operation Interrupt request signal Internal address bus Internal read signal Internal write signal Internal d...

Page 133: ...errupt Control Mode 2 Interrupt Control Mode 0 Interrupt Control Mode 2 Interrupt priority determination 1 3 Number of states until executing instruction ends 2 1 to 19 2 SI PC CCR EXR stacking SK to...

Page 134: ...etch Sh 1 8 12 4m 4 6 2m Instruction fetch SI 1 4 6 2m 2 3 m Stack manipulation SK 1 8 12 4m 4 6 2m Legend m Number of wait cycles in an external device access 5 6 5 DTC Activation by Interrupt The DT...

Page 135: ...earing the DTCE bit to 0 after the individual DTC data transfer Note that when the DTC performs a predetermined number of data transfers and the transfer counter indicates 0 an interrupt request is al...

Page 136: ...ERH of the DTC and the DISEL bit in MRB of the DTC Table 5 6 Interrupt Source Selection and Clear Control DTC Setting Interrupt Source Selection Clear Control DTCE DISEL DTC CPU 0 X 1 0 X 1 O Legend T...

Page 137: ...held The DTC is activated when the condition by which the activation source is held is cancelled CPUCPCE 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DTCP2 to DTCP0 The priority le...

Page 138: ...Disabled Table 5 8 shows a setting example of the priority control function over the DTC and the transfer request control state Table 5 8 Example of Priority Control Function Setting and Control State...

Page 139: ...rity over that interrupt interrupt exception handling will be executed for the interrupt with priority and another interrupt will be ignored The same also applies when an interrupt source flag is clea...

Page 140: ...of EEPMOV Instruction Interrupt operation differs between the EEPMOV B and the EEPMOV W instructions With the EEPMOV B instruction an interrupt request including NMI issued during the transfer is not...

Page 141: ...rrupts Source Flag of Peripheral Modules To clear an interrupt source flag by the CPU using an interrupt function of a peripheral module the flag must be read from after clearing within the interrupt...

Page 142: ...Section 5 Interrupt Controller Rev 2 00 Jun 28 2007 Page 120 of 666 REJ09B0311 0200...

Page 143: ...ltiplexed I O interface can be set An endian conversion function is provided to connect a device of little endian Basic bus interface This interface can be connected to the SRAM and ROM 2 state access...

Page 144: ...al write cycles and internal accesses can be executed in parallel Write accesses to the on chip peripheral module and on chip memory accesses can be executed in parallel External bus release function...

Page 145: ...request signal DTC bus mastership request signal External bus control signals Control register ABWCR ASTCR WTCRA WTCRB RDNCR CSACR IDLCR BCR1 BCR2 ENDIANCR SRAMCR BROMCR MPXCR ABWCR ASTCR WTCRA WTCRB...

Page 146: ...ntrol register ENDIANCR SRAM mode control register SRAMCR Burst ROM interface control register BROMCR Address data multiplexed I O control register MPXCR 6 2 1 Bus Width Control Register ABWCR ABWCR s...

Page 147: ...W R W R W R W R W R W R W Area 7 to 0 Bus Width Control These bits select whether the corresponding area is to be designated as 8 bit access space or 16 bit access space ABWHn ABWLn n 7 to 0 0 Settin...

Page 148: ...4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Bit Bit Name Initial Value R W Description 15 14 13 12 11 10 9 8 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Area 7 to 0 Acces...

Page 149: ...R W 15 0 R WTCRA WTCRB 14 W72 1 R W 13 W71 1 R W 12 W70 1 R W 11 0 R 10 W62 1 R W 9 W61 1 R W 8 W60 1 R W Bit Bit Name Initial Value R W 7 0 R 6 W52 1 R W 5 W51 1 R W 4 W50 1 R W 3 0 R 2 W42 1 R W 1...

Page 150: ...4 program wait cycles inserted 101 5 program wait cycles inserted 110 6 program wait cycles inserted 111 7 program wait cycles inserted 11 0 R Reserved This is a read only bit and cannot be modified 1...

Page 151: ...ogram wait cycles inserted 101 5 program wait cycles inserted 110 6 program wait cycles inserted 111 7 program wait cycles inserted 3 0 R Reserved This is a read only bit and cannot be modified 2 1 0...

Page 152: ...4 program wait cycles inserted 101 5 program wait cycles inserted 110 6 program wait cycles inserted 111 7 program wait cycles inserted 11 0 R Reserved This is a read only bit and cannot be modified 1...

Page 153: ...ogram wait cycles inserted 101 5 program wait cycles inserted 110 6 program wait cycles inserted 111 7 program wait cycles inserted 3 0 R Reserved This is a read only bit and cannot be modified 2 1 0...

Page 154: ...ese bits set the negation timing of the read strobe in a corresponding area read access As shown in figure 6 2 the read strobe for an area for which the RDNn bit is set to 1 is negated one half cycle...

Page 155: ...t ROM and address data multiplexed I O interface are to be extended Extending the assertion period of the CSn and address signals allows the setup time and hold time of read strobe RD and write strobe...

Page 156: ...e CSn and address assertion period Th is not extended 1 In access to area n the CSn and address assertion period Th is extended n 7 to 0 7 6 5 4 3 2 1 0 CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0...

Page 157: ...us Interface 3 State Access Space and RDNn 0 6 2 6 Idle Control Register IDLCR IDLCR specifies the idle cycle insertion conditions and the number of idle cycles Bit Bit Name Initial Value R W 15 1 R W...

Page 158: ...ycle is inserted 12 IDLS0 1 R W Idle Cycle Insertion 0 Inserts an idle cycle between the bus cycles when the external read cycle is followed by external write cycle 0 No idle cycle is inserted 1 An id...

Page 159: ...0 n 7 to 0 6 2 7 Bus Control Register 1 BCR1 BCR1 is used for selection of the external bus released state protocol enabling disabling of the write data buffer function and enabling disabling of the W...

Page 160: ...uld always be 0 9 WDBE 0 R W Write Data Buffer Enable The write data buffer function can be used for an external write cycle Note that a set value change may not be reflected to the external access im...

Page 161: ...always read as 0 The write value should always be 0 4 IBCCS 0 R W Internal Bus Cycle Control Select Selects the internal bus arbiter function 0 Releases the bus mastership according to the priority 1...

Page 162: ...rmat for the areas used as a program area or a stack area should be big endian Bit Bit Name Initial Value R W 7 LE7 0 R W 6 LE6 0 R W 5 LE5 0 R W 4 LE4 0 R W 3 LE3 0 R W 2 LE2 0 R W 1 0 R 0 0 R Bit Bi...

Page 163: ...W 11 BCSEL3 0 R W 10 BCSEL2 0 R W 9 BCSEL1 0 R W 8 BCSEL0 0 R W Bit Bit Name Initial Value R W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Bit Bit Name Initial Value R W Description 15 14 13 12 11...

Page 164: ...3 0 R 2 0 R 1 BSWD11 0 R W 0 BSWD10 0 R W Bit Bit Name Initial Value R W Description 15 BSRM0 0 R W Area 0 Burst ROM Interface Select Selects the area 0 bus interface When setting this bit to 1 clear...

Page 165: ...his bit to 1 clear the BCSEL1 bit in SRAMCR to 0 0 Basic bus interface or byte control SRAM interface 1 Burst ROM interface 6 5 4 BSTS12 BSTS11 BSTS10 0 0 0 R W R W R W Area 1 Burst Cycle Select Speci...

Page 166: ...0 0 0 0 0 R W R W R W R W R W Address Data Multiplexed I O Interface Select Specifies the bus interface for the corresponding area When setting the area n bit to 1 clear the BCSELn bit in SRAMCR to 0...

Page 167: ...eripheral bus A bus that accesses registers in the bus controller and interrupt controller and registers of peripheral modules such as SCI and timer External access cycle A bus that accesses external...

Page 168: ...WDT SCI A D D A B External bus interface The frequency of each synchronization clock I P and B is specified by the system clock control register SCKCR independently For further details see section 17...

Page 169: ...d at the beginning of each bus cycle For example if an external address access occurs when the frequency rate of I and B is n 1 0 to n 1 cycles of Tsy may be inserted If an internal peripheral module...

Page 170: ...2007 Page 148 of 666 REJ09B0311 0200 Divided clock synchronization cycle T1 Address I B AS CSn RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 Read LHWR LLWR Write T2 Tsy BS RD WR Figure 6 5 System Clock Ex...

Page 171: ...007 Page 149 of 666 REJ09B0311 0200 Divided clock synchronization cycle T1 Address I B AS CSn RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 Read LHWR LLWR Write T2 Tsy T3 BS RD WR Figure 6 6 System Clock E...

Page 172: ...bus is enabled Signal to hold the address during access to the address data multiplexed I O interface Read strobe RD Output Strobe signal indicating that the basic bus byte control SRAM burst ROM or a...

Page 173: ...selected Chip select 3 CS3 Output Strobe signal indicating that area 3 is selected Chip select 4 CS4 Output Strobe signal indicating that area 4 is selected Chip select 5 CS5 Output Strobe signal indi...

Page 174: ...ut Output O O O O O O O CS0 Output Output O O O O O CS1 O O O O O CS2 O O O CS3 O O O O O CS4 O O O O O CS5 O O O O O CS6 O O O O O CS7 O O O O O BS O O O O O O O RD WR O O O O O O O AS Output Output...

Page 175: ...ut for each area Figure 6 7 shows an area division of the 16 Mbyte address space For details on address map see section 3 MCU Operating Modes 16 Mbyte space Area 0 2 Mbytes Area 1 2 Mbytes Area 2 8 Mb...

Page 176: ...et and so the corresponding PFCR bits should be set to 1 when outputting signals CS1 to CS7 In on chip ROM enabled extended mode pins CS0 to CS7 are all placed in the input state after a reset and so...

Page 177: ...rnal Bus Interface Four types of external bus interfaces are provided and can be selected in area units Table 6 4 shows each interface name description and area name to be set for each interface Table...

Page 178: ...n the bus width of address data multiplexed I O space is 8 bits or 16 bits and the bus width for the byte control SRAM space is 16 bits The initial state of the bus width is specified by the operating...

Page 179: ...am wait cycles 0 to 7 number of CS extension cycles 0 1 2 number of external wait cycles by the WAIT pin b Byte Control SRAM Interface The number of access cycles in the byte control SRAM interface is...

Page 180: ...interface Table 6 6 Number of Access Cycles Tma 2 3 Tma 2 3 Th 0 1 Th 0 1 Th 0 1 Th 0 1 Th 0 1 Th 0 1 Th 0 1 Th 0 1 T1 1 T1 1 T1 1 T1 1 T1 1 T1 1 T1 1 T1 1 T2 1 T2 1 T2 1 T2 1 T2 1 T2 1 T2 1 T2 1 Tt 0...

Page 181: ...the external interface of area 0 Note Applied to the LSI version that incorporates the ROM Table 6 7 Area 0 External Interface Register Setting Interface BSRM0 of BROMCR BCSEL0 of SRAMCR Basic bus int...

Page 182: ...interface or byte control SRAM interface can be selected for area 2 by bit BCSEL2 in SRAMCR Table 6 9 shows the external interface of area 2 Table 6 9 Area 2 External Interface Register Setting Inter...

Page 183: ...ted for area 4 by bit MPXE4 in MPXCR and bit BCSEL4 in SRAMCR Table 6 11 shows the external interface of area 4 Table 6 11 Area 4 External Interface Register Setting Interface MPXE4 of MPXCR BCSEL4 of...

Page 184: ...1 Address data multiplexed I O interface 1 0 Setting prohibited 1 1 7 Area 6 Area 6 includes internal I O registers In external extended mode area 6 other than on chip I O register area is external a...

Page 185: ...le 6 14 shows the external interface of area 7 Table 6 14 Area 7 External Interface Register Setting Interface MPXE7 of MPXCR BCSEL7 of SRAMCR Basic bus interface 0 0 Byte control SRAM interface 0 1 A...

Page 186: ...the data alignment when the data endian format is specified as little endian Longword Access Address Access Count 23 7 15 8 0 7 Data Size Byte Byte Byte Byte Byte Byte Byte Byte Word 1 1st 1st 2nd 1s...

Page 187: ...n byte access for an even address is performed by using the upper byte data bus and byte access for an odd address is performed by using the lower byte data bus In little endian byte access for an eve...

Page 188: ...Byte Word Word Word Word Byte Byte Word 1 1 1 1st 1st 1st 1st 2nd 1st 2nd 1st 2nd 3rd 2 2 3 Bus Cycle Data Size 15 23 8 8 7 0 7 0 7 0 23 16 16 15 8 31 24 7 0 15 8 7 0 Even 2n 2n Odd Even 2n 1 Odd 2n 1...

Page 189: ...ble 6 15 shows the pins used for basic bus interface Table 6 15 I O Pins for Basic Bus Interface Name Symbol I O Function Bus cycle start BS Output Signal indicating that the bus cycle has started Add...

Page 190: ...ate access space When accessing 16 bit access space the upper byte data bus D15 to D8 is used for even addresses access and the lower byte data bus D7 to D0 is used for odd addresses No wait cycles ca...

Page 191: ...EJ09B0311 0200 Valid T1 T2 Address CSn AS RD High level High Z B Valid D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write Notes 1 n 0 to 7 2 When RDNn 0 BS RD WR Invalid Bus cycle Figure 6 15...

Page 192: ...f 666 REJ09B0311 0200 Valid Valid T1 T2 Address CSn AS RD B Bus cycle Valid Valid D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write BS RD WR Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 16 16 Bit...

Page 193: ...space the upper byte data bus D15 to D8 is used for even addresses and the lower byte data bus D7 to D0 is used for odd addresses Wait cycles can be inserted Valid Invalid T1 T2 T3 Address CSn AS RD H...

Page 194: ...J09B0311 0200 Invalid Valid T1 T2 T3 Address CSn AS RD High Z B Bus cycle D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write BS RD WR Notes 1 n 0 to 7 2 When RDNn 0 High level Valid Figure 6 1...

Page 195: ...666 REJ09B0311 0200 Valid Valid T1 T2 T3 Address CSn AS RD B Bus cycle Valid Valid D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write BS RD WR Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 19 16 Bit...

Page 196: ...for the corresponding pin is set to 1 wait input by means of the WAIT pin is enabled When the external address space is accessed in this state a program wait Tw is first inserted according to the WTCR...

Page 197: ...it by program wait T1 Address B AS CSn RD Data bus Read Read data LHWR LLWR Write data Write Notes 1 Upward arrows indicate the timing of WAIT pin sampling 2 n 0 to 7 3 RDNn 0 WAIT Data bus T1 Tpw Ttw...

Page 198: ...can be modified in area units by setting bits RDN7 to RDN0 in RDNCR to 1 Figure 6 21 shows an example of timing when the read strobe timing is changed in the basic bus 3 state access space Bus cycle...

Page 199: ...period can be set in area units With the CS assertion extension period in write access the data setup and hold times are less stringent since the write data is output to the data bus Figure 6 22 shows...

Page 200: ...8 2007 Page 178 of 666 REJ09B0311 0200 Th T1 T2 T3 Tt Address Bus cycle B AS CSn RD Data bus Read data Read LHWR LLWR Write data Write Note n 0 to 7 Data bus BS RD WR Figure 6 22 Example of Timing whe...

Page 201: ...asic bus interface regardless of the RDNCR settings and the RD WR signal is used as write enable WE 6 7 1 Byte Control SRAM Space Setting Byte control SRAM interface can be specified for areas 0 to 7...

Page 202: ...basic bus interface space or byte control SRAM space is accessed CSn CSn Chip select Output Strobe signal indicating that area n is selected RD RD Read strobe Output Output enable for the SRAM when t...

Page 203: ...l SRAM space is specified as a 2 state access space Data buses used for 16 bit access space is the same as those in basic bus interface No wait cycles can be inserted B Address D15 to D8 D7 to D0 High...

Page 204: ...is specified as a 3 state access space Data buses used for 16 bit access space is the same as those in the basic bus interface Wait cycles can be inserted B Address High level Bus cycle CSn AS T1 T2...

Page 205: ...wait cycles can be inserted automatically between T2 cycle and T3 cycle for the 3 state access space in area units according to the settings in WTCRA and WTCRB 2 Pin Wait Insertion For 3 state access...

Page 206: ...program wait T1 Address B AS UUB ULB CSn RD RD RD WR RD WR Data bus Read data Read BS Write data High level Write Notes 1 Upward arrows indicate the timing of WAIT pin sampling 2 n 0 to 7 WAIT Data b...

Page 207: ...ess space areas 0 and 1 can be designated as burst ROM space and burst ROM interfacing performed The burst ROM interface enables ROM with page access capability to be accessed at high speed Areas 1 an...

Page 208: ...6 17 I O Pins Used for Burst ROM Interface Name Symbol I O Function Bus cycle start BS Output Signal indicating that the bus cycle has started Address strobe AS Output Strobe signal indicating that an...

Page 209: ...7 are ignored From one to eight cycles can be selected for the burst cycle according to the settings of bits BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR Wait cycles cannot be inserted In addition...

Page 210: ...2 00 Jun 28 2007 Page 188 of 666 REJ09B0311 0200 T1 T2 T1 T1 B Upper address bus Lower address bus Data bus Full access Burst access CSn AS RD BS RD WR Note n 1 0 Figure 6 27 Example of Burst ROM Acce...

Page 211: ...by the CPU In this case the setting of the corresponding CSXTn bit in CSACR is ignored and an extension cycle can be inserted only before the full access cycle Note that no extension cycle can be inse...

Page 212: ...PH7 A7 D7 A7 D7 PH6 A6 D6 A6 D6 PH5 A5 D5 A5 D5 PH4 A4 D4 A4 D4 PH3 A3 D3 A3 D3 PH2 A2 D2 A2 D2 PH1 A1 D1 A1 D1 PH0 A0 D0 A0 D0 6 9 3 Data Bus The bus width of the address data multiplexed I O space...

Page 213: ...ting that the lower bytes D7 to D0 is valid when the address data multiplexed I O space is written D15 to D0 D15 to D0 Address data Input output Address and data multiplexed pins for the address data...

Page 214: ...ata cycle The data cycle is based on the basic bus interface timing specified by the ABWCR ASTCR WTCRA WTCRB RDNCR and CSACR Figures 6 28 and 6 29 show the basic access timings Tma1 Tma2 T2 T1 B Addre...

Page 215: ...f 666 REJ09B0311 0200 Tma1 Tma2 T2 T1 B Address bus D15 to D0 D15 to D0 Address cycle Bus cycle Data cycle CSn LHWR LLWR AH RD BS RD WR Note n 3 to 7 Address Read data Address Write data Read Write Fi...

Page 216: ...ng the ADDEX bit in MPXCR By inserting the Tmaw cycle the address setup for AH and the AH minimum pulse width can be assured Figure 6 30 shows the access timing when the address cycle is three cycles...

Page 217: ...control settings do not affect the address cycles 6 9 8 Read Strobe RD Timing In the address data multiplexed I O interface the read strobe timing of data cycles can be modified in the same way as in...

Page 218: ...assertion period extension timing Tma1 Tma2 T2 Tt T1 Th B Address bus D15 to D0 D15 to D0 Address cycle Bus cycle Data cycle CSn LHWR LLWR AH RD BS RD WR Note n 3 to 7 Address Read data Address Write...

Page 219: ...onflict is shown in a and an example of avoiding the data conflict by the CS assertion period extension cycle in b B Address bus Data bus Bus cycle A Bus cycle B CS AH RD a Without CS assertion period...

Page 220: ...n be inserted under the conditions shown above The number of idle cycles to be inserted should be specified to prevent data conflicts between the output data from a previously accessed device and data...

Page 221: ...ch Area Bit Settings IDLSn Area for Previous Access Insertion Condition n Setting IDLSELn 0 1 2 3 4 5 6 7 0 Invalid 0 A A A A A A A A Consecutive reads in different areas 1 1 1 B B B B B B B B 0 Inval...

Page 222: ...ample bus cycle A is a read cycle for ROM with a long output floating time and bus cycle B is a read cycle for SRAM each being located in a different area In a an idle cycle is not inserted and a conf...

Page 223: ...n this case In this example bus cycle A is a read cycle for ROM with a long output floating time and bus cycle B is a CPU write cycle In a an idle cycle is not inserted and a conflict occurs in bus cy...

Page 224: ...a CPU write cycle and bus cycle B is a read cycle from the SRAM In a an idle cycle is not inserted and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM device In...

Page 225: ...the external NOP cycles are counted as a part of the idle cycles Figure 6 37 shows an example of external NOP and idle cycle insertion T1 T2 T3 Tpw T1 T2 T3 Tpw Ti Ti Address bus No external access N...

Page 226: ...ween the RD signal in bus cycle A and the CS signal in bus cycle B Setting idle cycle insertion as in b however will prevent any overlap between the RD and CS signals In the initial state after reset...

Page 227: ...s inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 1 0 0 0 cycle inserted 0 1 2 cycle inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 0 Disabled Normal space read Normal space write 1 0 0 0 1...

Page 228: ...200 6 10 2 Pin States in Idle Cycle Table 6 23 shows the pin states in an idle cycle Table 6 23 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedan...

Page 229: ...al bus released state the CPU and DTC can access the internal space using the internal bus When either the CPU or DTC attempts to access the external address space it temporarily defers initiation of...

Page 230: ...6 24 shows pin states in the external bus released state Table 6 24 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance BS High impedance CSn n 7 to 0 Hi...

Page 231: ...he end of the external access cycle It takes two cycles or more after the low level of the BREQ signal is sampled 3 The BACK signal is driven low releasing bus to the external bus master 4 The BREQ si...

Page 232: ...ess cycles differs according to the register to be accessed When the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 n synchronization cycles using a clock d...

Page 233: ...s used When this function is used if an external address space write continues for two cycles or longer and there is an internal access next an external write only is executed in the first two cycles...

Page 234: ...ee table 6 26 in section 6 12 Figure 6 41 shows an example of the timing when the write data buffer function is used When this function is used if an internal I O register write continues for two cycl...

Page 235: ...he bus arbiter detects the bus masters bus request signals and if the bus is requested sends a bus request acknowledge signal to the bus master If there are bus requests from more than one bus master...

Page 236: ...d in multiple bus cycles Transfer data read or write by memory transfer instructions block transfer instructions or TAS instruction In the block transfer instructions the bus can be transferred in the...

Page 237: ...external address space When activating the external ROM specify the registers before external accesses other than the instruction fetch from the external ROM are generated 2 External Bus Release Func...

Page 238: ...mode is deferred and performed after the bus is recovered Also since clock oscillation halts in software standby mode if the BREQ signal goes low in this mode indicating an external bus release reques...

Page 239: ...The transfer source and destination addresses can be specified by 24 bits to select a 16 Mbyte address space directly Full address mode Transfer information is located on a 4 longword boundary The tra...

Page 240: ...interface Bus controller DTCCR Interrupt controller ACK REQ DTCVBR DTC DTC internal bus Peripheral bus Internal bus 32 bits External bus CPU interrupt request Interrupt source clear request 8 Registe...

Page 241: ...MRA MRB SAR DAR CRA and CRB cannot be directly accessed by the CPU The contents of these registers are stored in the data area as transfer information When a DTC activation request occurs the DTC rea...

Page 242: ...k transfer mode 11 Setting prohibited 5 4 Sz1 Sz0 Undefined Undefined DTC Data Transfer Size 1 and 0 Specify the size of data to be transferred 00 Byte size transfer 01 Word size transfer 10 Longword...

Page 243: ...CHNS Undefined DTC Chain Transfer Select Specifies the chain transfer condition If the following transfer is a chain transfer the completion check of the specified transfer count is not performed and...

Page 244: ...ecify a DAR operation after a data transfer 0X DAR is fixed DAR writeback is skipped 10 DAR is incremented after a transfer by 1 when Sz1 and Sz0 B 00 by 2 when Sz1 and Sz0 B 01 by 4 when Sz1 and Sz0...

Page 245: ...divided into multiple cycles to transfer data For details see section 7 5 1 Bus Cycle Division SAR cannot be accessed directly from the CPU 7 2 4 DTC Destination Address Register DAR DAR is a 32 bit...

Page 246: ...56 when CRAH CRAL H 00 In block transfer mode CRA is divided into two parts the upper eight bits CRAH and the lower eight bits CRAL CRAH holds the block size while CRAL functions as an 8 bit block siz...

Page 247: ...E12 0 R W 11 DTCE11 0 R W 10 DTCE10 0 R W 9 DTCE9 0 R W 8 DTCE8 0 R W Bit Bit Name Initial Value R W 7 DTCE7 0 R W 6 DTCE6 0 R W 5 DTCE5 0 R W 4 DTCE4 0 R W 3 DTCE3 0 R W 2 DTCE2 0 R W 1 DTCE1 0 R W 0...

Page 248: ...atch and this bit is set to 1 the DTC data transfer is started without reading a vector address and transfer information If the previous DTC activation is a chain transfer the vector address read and...

Page 249: ...not be written to The initial value of DTCVBR is H 00000000 Bit Bit Name Initial Value R W 31 0 R 30 0 R 29 0 R 28 0 R 27 0 R W 26 0 R W 25 0 R W 24 0 R W 23 0 R W 22 0 R W 21 0 R W 20 0 R W 19 0 R W...

Page 250: ...igure 7 2 The DTC reads the start address of transfer information from the vector table according to the activation source and then reads the transfer information from the start address Figure 7 3 sho...

Page 251: ...or Address and Transfer Information Table 7 1 shows correspondence between the DTC activation source and vector address Table 7 1 Interrupt Sources DTC Vector Addresses and Corresponding DTCEs Origin...

Page 252: ...EB1 TGI4B 107 H 5AC DTCEB0 TPU_5 TGI5A 110 H 5B8 DTCEC15 TGI5B 111 H 5BC DTCEC14 TMR_0 CMIA0 116 H 5D0 DTCEC13 CMIB0 117 H 5D4 DTCEC12 TMR_1 CMIA1 119 H 5DC DTCEC11 CMIB1 120 H 5E0 DTCEC10 TMR_2 CMIA2...

Page 253: ...nsferred at One Transfer Request Memory Address Increment or Decrement Transfer Count Normal 1 byte word longword Incremented decremented by 1 2 or 4 or fixed 1 to 65536 Repeat 1 1 byte word longword...

Page 254: ...r data Update transfer information Update the start address of transfer information Write transfer information CHNE 1 Transfer counter 0 or DISEL 1 Clear activation source flag End CHNS 0 Transfer cou...

Page 255: ...ransfer mode or CRB in block transfer mode 2 When the contents of the CRAH is written to the CRAL in repeat transfer mode 7 5 1 Bus Cycle Division When the transfer data size is word and the SAR and D...

Page 256: ...fer is specified as word Example 2 When an odd address and address 4n are specified in SAR and DAR respectively and when the data size of transfer is specified as longword Example 3 When address 4n 2...

Page 257: ...performed Figure 7 6 shows the transfer information read skip timing To modify the vector table and transfer information temporarily clear the RRS bit to 0 modify the vector table and transfer informa...

Page 258: ...pped Registers SM1 DM1 SAR DAR 0 0 Skipped Skipped 0 1 Skipped Written back 1 0 Written back Skipped 1 1 Written back Written back 7 5 4 Normal Transfer Mode In normal transfer mode one operation tran...

Page 259: ...o 256 transfers can be specified When the specified number of transfers ends the transfer counter and address register specified as the repeat area is restored to the initial state and transfer is rep...

Page 260: ...1 SAR initial value DAR Destination address Incremented decremented fixed DTS 0 DAR initial value DTS 1 Incremented decremented fixed CRAH Transfer count storage CRAH CRAH CRAL Transfer count A CRAL...

Page 261: ...fers can be specified When the specified number of transfers ends an interrupt is requested to the CPU Table 7 8 lists the register function in block transfer mode Figure 7 9 shows the memory map in b...

Page 262: ...CHNE set to 1 an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting the DISEL bit to 1 and the interrupt source flag for the activation source...

Page 263: ...read Transfer information read Data transfer Transfer information write Figure 7 11 DTC Operation Timing Example of Short Address Mode in Normal Transfer Mode or Repeat Transfer Mode Clock Address DT...

Page 264: ...information write Transfer information read Data transfer Transfer information write Figure 7 13 DTC Operation Timing Example of Short Address Mode in Chain Transfer Clock Address DTC activation requ...

Page 265: ...3 6 2 7 1 3 6 2 7 1 1 0 1 Repeat 1 0 1 4 2 3 3 0 1 3 2 3 2 4 1 5 3 6 2 7 1 3 6 2 7 1 1 0 1 Block transfer 1 0 1 4 2 3 3 0 1 3 2 3 2 4 1 5 3 P 6 2 P 7 1 P 3 P 6 2 P 7 1 P 1 0 1 Legend P Block size CRA...

Page 266: ...to 7 For details see section 6 Bus Controller BSC The number of execution cycles is calculated from the formula below Note that means the sum of all transfers activated by one activation event the num...

Page 267: ...corresponding to the DTC activation interrupt source to 1 For the correspondence of interrupts and DTCER refer to table 7 1 The bit in DTCER may be set to 1 on the second or later transfer In this ca...

Page 268: ...interrupt at the DTC vector address 3 Set the corresponding bit in DTCER to 1 4 Set the SCI to the appropriate receive mode Set the RIE bit in SCR to 1 to enable the receive end RXI interrupt Since t...

Page 269: ...source address incrementing SM1 1 SM0 0 fixed destination address DM1 DM0 0 normal mode MD1 MD0 0 and word size Sz1 0 Sz0 1 Set the data table start address in SAR the TGRA address in DAR and the data...

Page 270: ...setting the transfer destination address for the first data transfer Use the upper eight bits of DAR in the first transfer information area as the transfer destination Set CHNE DISEL 0 If the above in...

Page 271: ...a transfers or a data transfer for which the DISEL bit was set to 1 In the case of interrupt activation the interrupt set as the activation source is generated These interrupts to the CPU are subject...

Page 272: ...ion sources on the other hand are cleared when the DTC reads or writes to the relevant register Therefore when the DTC is activated by an interrupt or activation source if a read write of the relevant...

Page 273: ...s Ports 2 and F include an open drain control register ODR that controls on off of the output buffer PMOSs All of the I O ports can drive a single TTL load and capacitive loads up to 30 pF All of the...

Page 274: ...MO1 TxD1 All input functions General I O port also functioning as interrupt inputs PPG outputs TPU I Os TMR I Os and SCI I Os 5 P25 TIOCA4 TMCI1 RxD1 PO5 P25 TIOCA4 TMCI1 4 P24 TIOCB4 SCK1 TIOCA4 TMRI...

Page 275: ...35 TIOCB1 TIOCA1 TCLKC A PO13 All input functions 4 P34 TIOCA1 PO12 All input functions 3 P33 TIOCD0 TIOCC0 TCLKB A PO11 All input functions 2 P32 TIOCC0 TCLKA A PO10 All input functions 1 P31 TIOCB0...

Page 276: ...neral I O port also functioning as TMR I Os SCI I Os and interrupt inputs 4 P64 TMCI3 TMCI3 3 P63 TMRI3 IRQ11 B TMRI3 IRQ11 B 2 P62 SCK4 IRQ10 B TMO2 IRQ10 B 1 P61 TMCI2 RxD4 IRQ9 B TMCI2 IRQ9 B 0 P60...

Page 277: ...put Function 7 Port B 6 5 General I O port also functioning as bus control outputs 4 3 PB3 CS3 CS7 A 2 PB2 CS2 A CS6 A 1 PB1 CS1 CS2 B CS5 A CS6 B CS7 B 0 PB0 CS0 CS4 A CS5 B 7 A7 O Port D 6 A6 5 A5 G...

Page 278: ...oning as address outputs 4 A20 3 A19 2 A18 1 A17 0 A16 7 D7 2 O Port H 6 D6 2 5 D5 2 General I O port also functioning as bi directional data bus 4 D4 2 3 D3 2 2 D2 2 1 D1 2 0 D0 2 7 PI7 D15 2 O Port...

Page 279: ...Port 3 8 O O O O Port 5 8 O O Port 6 1 6 O O O O Port A 8 O O O O Port B 2 4 O O O O Port D 8 O O O O O Port E 8 O O O O O Port F 8 O O O O O O Port H 8 O O O O O Port I 8 O O O O O Legend O Register...

Page 280: ...setting the corresponding DDR bit to 1 the corresponding pin functions as an input port by clearing the corresponding DDR bit to 0 The initial DDR values are shown in table 8 3 Bit Bit Name Initial V...

Page 281: ...s 8 1 3 Port Register PORTn n 1 to 3 5 6 A B D to F H and I PORT is an 8 bit read only register that reflects the port pin status A write to PORT is invalid When PORT is read the DR bits that correspo...

Page 282: ...the pin state is not reflected to the peripheral modules When PORT is read the pin status is always read regardless of the ICR value If ICR is modified an internal edge may occur depending on the pin...

Page 283: ...n5PCR 0 R W 4 Pn4PCR 0 R W 3 Pn3PCR 0 R W 2 Pn2PCR 0 R W 1 Pn1PCR 0 R W 0 Pn0PCR 0 R W Table 8 4 Input Pull Up MOS State Port Pin State Reset Hardware Standby Mode Software Standby Mode Other Operatio...

Page 284: ...Control This section describes the output priority of each pin The name of each peripheral module pin is followed by _OE This for example MIOCA4_OE indicates whether the output of the corresponding fu...

Page 285: ...output 1 P16 input initial setting 0 3 P15 IRQ5 A TCLKB B The pin function is switched as shown below according to the P15DDR bit setting Setting I O Port Module Name Pin Function P15DDR I O port P15...

Page 286: ...6 P12 SCK2 IRQ2 A The pin function is switched as shown below according to the combination of the SCI register setting and P12DDR bit setting Setting SCI I O Port Module Name Pin Function SCK2_OE P12D...

Page 287: ...ame Pin Function TxD2_OE P10DDR SCI TxD2 output 1 P10 output 0 1 I O port P10 input initial setting 0 0 8 2 2 Port 2 1 P27 PO7 TIOCA5 TIOCB5 The pin function is switched as shown below according to th...

Page 288: ...O1_OE TxD1_OE PO6_OE P26DDR TPU TIOCA5 output 1 TMR TMO1 output 0 1 SCI TxD1 output 0 0 1 PPG PO6 output 0 0 0 1 P26 output 0 0 0 0 1 I O port P26 input initial setting 0 0 0 0 0 3 P25 PO5 TIOCA4 TMCI...

Page 289: ...ion TIOCB4_OE SCK1_OE PO4_OE P24DDR TPU TIOCB4 output 1 SCI SCK1 output 0 1 PPG PO4 output 0 0 1 P24 output 0 0 0 1 I O port P24 input initial setting 0 0 0 0 5 P23 PO3 TIOCC3 TIOCD3 IRQ11 A The pin f...

Page 290: ...MO0_OE TxD0_OE PO2_OE P22DDR TPU TIOCC3 output 1 TMR TMO0 output 0 1 SCI TxD0 output 0 0 1 PPG PO2 output 0 0 0 1 P22 output 0 0 0 0 1 I O port P22 input initial setting 0 0 0 0 0 7 P21 PO1 TIOCA3 TMC...

Page 291: ...TIOCB3_OE SCK0_OE PO0_OE P20DDR TPU TIOCB3 output 1 PPG PO0 output 0 1 SCI SCK0 output 0 0 1 P20 output 0 0 0 1 I O port P20 input initial setting 0 0 0 0 8 2 3 Port 3 1 P37 PO15 TIOCA2 TIOCB2 TCLKD A...

Page 292: ...ction TIOCA2_OE PO14_OE P36DDR TPU TIOCA2 output 1 PPG PO14 output 0 1 P36 output 0 0 1 I O port P36 input initial setting 0 0 0 3 P35 PO13 TIOCA1 TIOCB1 TCLKC A The pin function is switched as shown...

Page 293: ...ction TIOCA1_OE PO12_OE P34DDR TPU TIOCA1 output 1 PPG PO12 output 0 1 P34 output 0 0 1 I O port P34 input initial setting 0 0 0 5 P33 PO11 TIOCC0 TIOCD0 TCLKB A The pin function is switched as shown...

Page 294: ...me Pin Function TIOCC0_OE PO10_OE P32DDR TPU TIOCC0 output 1 PPG PO10 output 0 1 P32 output 0 0 1 I O port P32 input initial setting 0 0 0 7 P31 PO9 TIOCA0 TIOCB0 The pin function is switched as shown...

Page 295: ...U and PPG register settings and P30DDR bit setting Setting TPU PPG I O Port Module Name Pin Function TIOCA0_OE PO8_OE P30DDR TPU TIOCA0 output 1 PPG PO8 output 0 1 P30 output 0 0 1 I O port P30 input...

Page 296: ...OE P65DDR TMR TMO3 output 1 P65 output 0 1 I O port P65 input initial setting 0 0 2 P64 TMCI3 The pin function is switched as shown below according to the P64DDR bit setting Setting I O Port Module Na...

Page 297: ...P62 output 0 0 1 I O port P62 input initial setting 0 0 0 5 P61 TMCI2 RxD4 IRQ9 B The pin function is switched as shown below according to the P61DDR bit setting Setting I O Port Module Name Pin Funct...

Page 298: ...switches according to the POSEL1 bit in SCKCR For details see section 17 1 1 System Clock Control Register SCKCR 2 PA6 AS AH BS B The pin function is switched as shown below according to the combinat...

Page 299: ...wn below according to the combination of bus controller register port function control register PFCR and the PA4DDR bit settings Setting Bus Controller I O Port Module Name Pin Function LUB_OE LHWR_OE...

Page 300: ...t 1 Bus controller LLWR output initial setting 1 Note If the byte control SRAM space is accessed this pin functions as the LLB output otherwise the LLWR 6 PA2 BREQ WAIT The pin function is switched as...

Page 301: ...ntrol SRAM Selection RD WR _OE PA1DDR BACK output 1 0 1 Bus controller RD WR output 0 0 1 PA1 output 0 0 0 1 I O port PA1 input initial setting 0 0 0 0 8 PA0 BREQO BS A The pin function is switched as...

Page 302: ...Name Pin Function CS3_OE CS7A_OE PB3DDR Bus controller CS3 output 1 CS7 A output 1 I O port PB3 output 0 0 1 PB3 input initial setting 0 0 0 2 PB2 CS2 A CS6 A The pin function is switched as shown bel...

Page 303: ..._OE PB1DDR CS1 output 1 Bus controller CS2 B output 1 CS5 A output 1 CS6 B output 1 CS7 B output 1 I O port PB1 output 0 0 0 0 0 1 PB1 input initial setting 0 0 0 0 0 0 4 PB0 CS0 CS4 A CS5 B The pin f...

Page 304: ...pin function is always address output Setting I O Port Module Name Pin Function PDnDDR Bus controller Address output Legend n 0 to 7 8 2 9 Port E 1 PE7 A15 PE6 A14 PE5 A13 PE4 A12 PE3 A11 PE2 A10 PE1...

Page 305: ...output CS6 C output CS7 C output PF7DDR A23 output 1 CS4 C output 0 1 CS5 C output 0 1 CS6 C output 0 1 Bus controller CS7 C output 0 1 PF7 output 0 0 0 0 0 1 I O port PF7 input initial setting 0 0 0...

Page 306: ...ngs Setting I O Port Module Name Pin Function A21_OE CS5D_OE PF5DDR Bus controller A21 output 1 CS5 D output 0 1 PF5 output 0 0 1 I O port PF5 input initial setting 0 0 0 4 PF4 A20 The pin function is...

Page 307: ...tting I O Port Module Name Pin Function PF2DDR Bus controller A18 output 7 PF1 A17 The pin function is always address output Setting I O Port Module Name Pin Function PF1DDR Bus controller A17 output...

Page 308: ...ntroller Data I O initial setting 8 2 12 Port I 1 PI7 D15 PI6 D14 PI5 D13 PI4 D12 PI3 D11 PI2 D10 PI1 D9 PI0 D8 The pin function is switched as shown below according to the combination of operating mo...

Page 309: ...OR5 IOB3 0 TPU TIOR5 IOB 1 0 01 10 11 PO7_OE PO7 NDERL NDER7 1 6 TIOCA5_OE TIOCA5 TPU TIOR5 IOA3 0 TPU TIOR5 IOA 1 0 01 10 11 TMO1_OE TMO1 TCSR OS3 2 01 10 11 or TCSR OS 1 0 01 10 11 TxD1_OE TxD1 SCR...

Page 310: ...1 or SCR RE 1 while SMR GM 0 SCR CKE 1 0 01 or while SMR GM 1 When SCMR SMIF 0 SCR TE 1 or SCR RE 1 while SMR C A 0 SCR CKE 1 0 01 or while SMR C A 1 SCR CKE 1 0 PO0_OE PO0 NDERL NDER0 1 P3 7 TIOCB2_...

Page 311: ...TCSR OS 1 0 01 10 11 SCK4_OE SCK4 When SCMR SMIF 1 SCR TE 1 or SCR RE 1 while SMR GM 0 SCR CKE 1 0 01 or while SMR GM 1 When SCMR SMIF 0 SCR TE 1 or SCR RE 1 while SMR C A 0 SCR CKE 1 0 01 or while S...

Page 312: ...B 00 PFCR0 CS6E 1 1 CS1_OE CS1 PFCR0 CS1E 1 CS2B_OE CS2 PFCR2 CS2S 1 PFCR0 CS2E 1 CS5A_OE CS5 PFCR1 CS5S A B 00 PFCR0 CS5E 1 CS6B_OE CS6 PFCR1 CS6S A B 01 PFCR0 CS6E 1 CS7B_OE CS7 PFCR1 CS7S A B 01 PF...

Page 313: ...FCR1 CS7S A B 10 PFCR0 CS7E 1 6 A22_OE CS6D_OE A22 CS6 PFCR4 A22E 1 PFCR1 CS6S A B 11 PFCR0 CS6E 1 5 A21_OE CS5D_OE A21 CS5 PFCR4 A21E 1 PFCR1 CS5S A B 11 PFCR0 CS5E 1 4 A20_OE A20 3 A19_OE A19 2 A18_...

Page 314: ...function control register 9 PFCR9 Port function control register B PFCRB Port function control register C PFCRC 8 3 1 Port Function Control Register 0 PFCR0 PFCR0 enables disables the CS output Bit Bi...

Page 315: ...Specifies pin PB3 as CS7 A output 01 Specifies pin PB1 as CS7 B output 10 Specifies pin PF7 as CS7 C output 11 Setting prohibited 5 4 CS6SA CS6SB 0 0 R W R W CS6 Output Pin Select Selects the output p...

Page 316: ...3 Chip Select Signals 8 3 3 Port Function Control Register 2 PFCR2 PFCR1 selects the CS output pin enables disables bus control I O and selects the bus control I O pins Bit Bit Name Initial Value R W...

Page 317: ...R output 0 Disables the RD WR output 1 Enables the RD WR output 1 ASOE 1 R W AS Output Enable Enables disables the AS output 0 Specifies pin PA6 as I O port 1 Specifies pin PA6 as AS output pin 0 0 R...

Page 318: ...ial Value R W Description 7 A23E 0 R W Address A23 Enable Enables disables the address output A23 0 Disables the A23 output 1 Enables the A23 output 6 A22E 0 R W Address A22 Enable Enables disables th...

Page 319: ...R W LHWR Output Enable Enables disables LHWR output valid in external extended mode 0 Specifies pin PA4 as I O port 1 Specifies pin PA4 as LHWR output pin 5 1 R W Reserved This bit is always read as 1...

Page 320: ...put and input capture 1 Specifies P27 as input capture input and P26 as output compare 6 TPUMS4 0 R W TPU I O Pin Multiplex Function Select Selects TIOCA4 function 0 Specifies P25 as output compare ou...

Page 321: ...n Select Selects TIOCA1 function 0 Specifies P34 as output compare output and input capture 1 Specifies P35 as input capture input and P34 as output compare 1 TPUMS0A 0 R W TPU I O Pin Multiplex Funct...

Page 322: ...ways read as 0 The write value should always be 0 3 ITS11 0 R W IRQ11 Pin Select Selects an input pin for IRQ11 0 Selects pin P23 as IRQ11 A input 1 Selects pin P63 as IRQ11 B input 2 ITS10 0 R W IRQ1...

Page 323: ...or IRQ7 0 Selects pin P17 as IRQ7 A input 1 Selects pin P57 as IRQ7 B output 6 ITS6 0 R W IRQ6 Pin Select Selects an input pin for IRQ6 0 Selects pin P16 as IRQ6 A input 1 Selects pin P56 as IRQ6 B ou...

Page 324: ...ts an input pin for IRQ2 0 Selects pin P12 as IRQ2 A input 1 Selects pin P52 as IRQ2 B output 1 ITS1 0 R W IRQ1 Pin Select Selects an input pin for IRQ1 0 Selects pin P11 as IRQ1 A input 1 Selects pin...

Page 325: ...t disable the input function for the pin by setting ICR 8 4 2 Notes on Port Function Control Register PFCR Settings The port function controller controls the I O ports To set the input output to each...

Page 326: ...Section 8 I O Ports Rev 2 00 Jun 28 2007 Page 304 of 666 REJ09B0311 0200...

Page 327: ...lear operation Synchronous operations Multiple timer counters TCNT can be written to simultaneously Simultaneous clearing by compare match and input capture possible Simultaneous input output for regi...

Page 328: ...RD_3 I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare matc...

Page 329: ...re match or input capture Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4...

Page 330: ...TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 3 Channel 4 Channel 5 Interrupt request signals Channel 0 Channel 1 Channel 2 Internal data bus A D conversion start request...

Page 331: ...in 0 TIOCD0 I O TGRD_0 input capture input output compare output PWM output pin TIOCA1 I O TGRA_1 input capture input output compare output PWM output pin 1 TIOCB1 I O TGRB_1 input capture input outpu...

Page 332: ..._0 Timer general register B_0 TGRB_0 Timer general register C_0 TGRC_0 Timer general register D_0 TGRD_0 Channel 1 Timer control register_1 TCR_1 Timer mode register_1 TMDR_1 Timer I O control registe...

Page 333: ...general register D_3 TGRD_3 Channel 4 Timer control register_4 TCR_4 Timer mode register_4 TMDR_4 Timer I O control register _4 TIOR_4 Timer interrupt enable register_4 TIER_4 Timer status register_4...

Page 334: ...1 and 0 These bits select the input clock edge For details see table 9 5 When the input clock is counted using both edges the input clock period is halved e g P 4 both edges P 2 rising edge If phase...

Page 335: ...ther channel performing synchronous clearing synchronous operation 1 1 0 0 TCNT clearing disabled 1 0 1 TCNT cleared by TGRC compare match input capture 2 1 1 0 TCNT cleared by TGRD compare match inpu...

Page 336: ...cleared by counter clearing for another channel performing synchronous clearing synchronous operation 1 Notes 1 Synchronous operation is selected by setting the SYNC bit in TSYR to 1 2 Bit 7 is reser...

Page 337: ...nts on TCLKB pin input 1 1 0 External clock counts on TCLKC pin input 0 1 1 1 External clock counts on TCLKD pin input Table 9 7 TPSC2 to TPSC0 Channel 1 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 De...

Page 338: ...clock counts on TCLKB pin input 1 1 0 External clock counts on TCLKC pin input 2 1 1 1 Internal clock counts on P 1024 Note This setting is ignored when channel 2 is in phase counting mode Table 9 9...

Page 339: ...ternal clock counts on P 1024 4 1 1 1 Counts on TCNT5 overflow underflow Note This setting is ignored when channel 4 is in phase counting mode Table 9 11 TPSC2 to TPSC0 Channel 5 Channel Bit 2 TPSC2 B...

Page 340: ...When TGRD is used as a buffer register TGRD input capture output compare is not generated In channels 1 2 4 and 5 which have no TGRD bit 5 is reserved It is always read as 0 and cannot be modified 0...

Page 341: ...ways be written to MD2 9 3 3 Timer I O Control Register TIOR TIOR controls TGR The TPU has eight TIOR registers two each for channels 0 and 3 and one each for channels 1 2 4 and 5 Care is required sin...

Page 342: ...ial Value R W Description 7 6 5 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 R W R W R W R W I O Control B3 to B0 Specify the function of TGRB For details see tables 9 13 9 15 9 16 9 17 9 19 and 9 20 3 2 1 0 IOA3 IO...

Page 343: ...at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is...

Page 344: ...1 1 Output compare register 2 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD0 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCD0 p...

Page 345: ...atch 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is...

Page 346: ...Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare m...

Page 347: ...at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is...

Page 348: ...1 1 Output compare register 2 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCD3 p...

Page 349: ...Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output To...

Page 350: ...Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare m...

Page 351: ...pare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial out...

Page 352: ...t compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is T...

Page 353: ...ut disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle...

Page 354: ...Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare m...

Page 355: ...pare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial out...

Page 356: ...at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is...

Page 357: ...Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output To...

Page 358: ...Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare m...

Page 359: ...y TGRA input capture compare match 0 A D conversion start request generation disabled 1 A D conversion start request generation enabled 6 1 R Reserved This is a read only bit and cannot be modified 5...

Page 360: ...errupt requests TGIC by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3 In channels 1 2 4 and 5 bit 2 is reserved It is always read as 0 and cannot be modified 0 Interrupt reques...

Page 361: ...in channels 1 2 4 and 5 In channels 0 and 3 bit 7 is reserved It is always read as 1 and cannot be modified 0 TCNT counts down 1 TCNT counts up 6 1 R Reserved This is a read only bit and cannot be mo...

Page 362: ...W Input Capture Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3 In channels 1 2 4 and 5 bit 3 is reserved It is always read...

Page 363: ...DISEL bit in MRB of DTC is 0 When 0 is written to TGFC after reading TGFC 1 When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled be sure to read the flag a...

Page 364: ...e TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Clearing conditions When DTC is acti...

Page 365: ...0 R W 1 0 R W 0 0 R W 9 3 7 Timer General Register TGR TGR is a 16 bit readable writable register with a dual function as output compare and input capture registers The TPU has 16 TGR registers four e...

Page 366: ...W Description 7 6 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 5 4 3 2 1 0 CST5 CST4 CST3 CST2 CST1 CST0 0 0 0 0 0 0 R W R W R W R W R W R W Counter Start 5 t...

Page 367: ...1 0 SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 0 0 0 0 0 0 R W R W R W R W R W R W Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels When...

Page 368: ...e Figure 9 2 shows an example of the count operation setting procedure Select counter clock Operation selection Select counter clearing source Periodic counter Set period Start count Periodic counter...

Page 369: ...s free running counter operation TCNT value H FFFF H 0000 CST bit TCFV Time Figure 9 3 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for th...

Page 370: ...g procedure for waveform output by compare match Figure 9 5 shows an example of the setting procedure for waveform output by a compare match Select waveform output mode Output selection Set output tim...

Page 371: ...level does not change TCNT value H FFFF H 0000 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 9 6 Example of 0 Output 1 Output Operation Figure 9 7 shows...

Page 372: ...ut capture input for channels 0 and 3 P 1 should not be selected as the counter input clock used for input capture input Input capture will not be generated if P 1 is selected a Example of setting pro...

Page 373: ...d falling edges have been selected as the TIOCA pin input capture input edge falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has bee...

Page 374: ...ronous presetting Synchronous presetting 1 2 Synchronous clearing Select counter clearing source Counter clearing 3 Start count 5 Set synchronous counter clearing Synchronous clearing 4 Start count 5...

Page 375: ...aring has been set for the channel 1 and 2 counter clearing source Three phase PWM waveforms are output from pins TIOCA0 TIOCA1 and TIOCA2 At this time synchronous presetting and synchronous clearing...

Page 376: ...ows the register combinations used in buffer operation Table 9 29 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register TGRA_0 TGRC_0 0 TGRB_0 TGRD_0 TGRA_3 TGRC_3 3...

Page 377: ...TCNT Input capture signal Figure 9 13 Input Capture Buffer Operation 1 Example of Buffer Operation Setting Procedure Figure 9 14 shows an example of the buffer operation setting procedure Select TGR f...

Page 378: ...TGRA This operation is repeated each time compare match A occurs For details on PWM modes see section 9 4 5 PWM Modes TCNT value TGRB_0 H 0000 TGRC_0 TGRA_0 H 0200 H 0520 TIOCA H 0200 H 0450 H 0520 H...

Page 379: ...n works by counting the channel 1 channel 4 counter clock at overflow underflow of TCNT_2 TCNT_5 as set in bits TPSC2 to TPSC0 in TCR Underflow occurs only when the lower 16 bit TCNT is in phase count...

Page 380: ...the count operation 1 2 1 2 Figure 9 17 Example of Cascaded Operation Setting Procedure 2 Examples of Cascaded Operation Figure 9 18 illustrates the operation when counting upon TCNT_2 overflow underf...

Page 381: ...m in the range of 0 to 100 duty cycle Designating TGR compare match as the counter clearing source enables the cycle to be set in that register All channels can be designated for PWM mode independentl...

Page 382: ...when a compare match occurs In PWM mode 2 a maximum 15 phase PWM output is possible by combined use with synchronous operation The correspondence between PWM output pins and registers is shown in tab...

Page 383: ...used as the TCNT clearing source 3 Use TIOR to designate TGR as an output compare register and select the initial value and output value 4 Set the cycle in TGR selected in 2 and set the duty in the ot...

Page 384: ...hannels 0 and 1 TGRB_1 compare match is set as the TCNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGRA_0 to TGRD_0 TGRA_1 to outpu...

Page 385: ...RB changed TGRB changed TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB changed TGRB changed TGRB changed Output does not change when compare matches in cycle register and duty register occur sim...

Page 386: ...hile TCNT is counting up the TCFV flag in TSR is set when underflow occurs while TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag provid...

Page 387: ...ting mode 1 operation and table 9 33 summarizes the TCNT up down count conditions TCNT value Time Down count Up count TCLKA channels 1 and 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channel...

Page 388: ...nd 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 9 26 Example of Phase Counting Mode 2 Operation Table 9 34 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Chan...

Page 389: ...nd 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 9 27 Example of Phase Counting Mode 3 Operation Table 9 35 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Chan...

Page 390: ...lue TCLKA channels 1 and 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 9 28 Example of Phase Counting Mode 4 Operation Table 9 36 Up Down Count Conditions in Phase Coun...

Page 391: ...sition control cycle TGRB_0 is used for input capture with TGRB_0 and TGRD_0 operating in buffer mode The channel 1 counter input clock is designated as the TGRB_0 input capture source and the pulse w...

Page 392: ...by clearing the status flag to 0 Relative channel priority levels can be changed by the interrupt controller but the priority within a channel is fixed For details see section 5 Interrupt Controller...

Page 393: ...capture compare match TGFC_3 Possible TGI3D TGRD_3 input capture compare match TGFD_3 Possible TCI3V TCNT_3 overflow TCFV_3 Not possible 4 TGI4A TGRA_4 input capture compare match TGFA_4 Possible TGI...

Page 394: ...he occurrence of a TCNT underflow on a channel The interrupt request is cleared by clearing the TCFU flag to 0 The TPU has four underflow interrupts one each for channels 1 2 4 and 5 9 6 DTC Activatio...

Page 395: ...ming in internal clock operation and figure 9 31 shows TCNT count timing in external clock operation P Internal clock TCNT input clock TCNT Falling edge Rising edge N 1 N 1 N 2 N Falling edge Figure 9...

Page 396: ...set in TIOR is output at the output compare output pin TIOC pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 9 32 shows o...

Page 397: ...when counter clearing by compare match occurrence is specified and figure 9 35 shows the timing when counter clearing by input capture occurrence is specified P TCNT N TGR Compare match signal Counter...

Page 398: ...peration Timing Figures 9 36 and 9 37 show the timings in buffer operation P n 1 n TGRA TGRB TGRC TGRD N N Compare match signal TCNT n Figure 9 36 Buffer Operation Timing Compare Match P TCNT N 1 N In...

Page 399: ...and the TGI interrupt request signal timing TGR Compare match signal P TCNT input clock TCNT N 1 N N TGF flag TGI interrupt Figure 9 38 TGI Interrupt Timing Compare Match 2 TGF Flag Setting Timing in...

Page 400: ...interrupt request signal timing Figure 9 41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence and the TCIU interrupt request signal timing H FFFF P TCNT input clock TCNT ov...

Page 401: ...T1 T2 Figure 9 42 Timing for Status Flag Clearing by CPU The status flag and interrupt request signal are cleared in synchronization with P after the DTC transfer has started as shown in figure 9 43 I...

Page 402: ...is masked DTC read cycle DTC write cycle T1 T2 T1 T2 Figure 9 43 Timing for Status Flag Clearing by DTC Activation 1 P Address Status flag Interrupt request signal Source address Destination address...

Page 403: ...st 1 5 states in the case of single edge detection and at least 2 5 states in the case of both edge detection The TPU will not operate properly with a narrower pulse width In phase counting mode the p...

Page 404: ...ctual counter frequency is given by the following formula f P N 1 f P N Counter frequency Operating frequency TGR set value 9 9 4 Conflict between TCNT Write and Clear Operations If the counter cleari...

Page 405: ...e M TCNT write data TCNT address Figure 9 47 Conflict between TCNT Write and Increment Operations 9 9 6 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR...

Page 406: ...a Figure 9 49 shows the timing in this case TGR Compare match signal P N Address Write M TGR write cycle Buffer register address Data written to buffer register M Buffer register T1 T2 Figure 9 49 Con...

Page 407: ...R Read and Input Capture 9 9 9 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle the input capture operation takes precedence a...

Page 408: ...nerated in the T2 state of a buffer register write cycle the buffer operation takes precedence and the write to the buffer register is not performed Figure 9 52 shows the timing in this case TCNT P In...

Page 409: ...R Counter clear signal H 0000 P TCNT input clock TCNT TGF flag TCFV flag H FFFF Disabled Figure 9 53 Conflict between Overflow and Counter Clearing 9 9 12 Conflict between TCNT Write and Overflow Unde...

Page 410: ...pin with the TIOCB1 I O pin and the TCLKD input pin with the TIOCB2 I O pin When an external clock is input compare match output should not be performed from a multiplexed pin 9 9 14 Interrupts and Mo...

Page 411: ...mer pulse unit TPU as a time base The PPG pulse outputs are divided into 4 bit groups groups 3 to 0 that can operate both simultaneously and independently Figure 10 1 shows a block diagram of the PPG...

Page 412: ...RL PODRH PODRL PPG output mode register PPG output control register Next data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data...

Page 413: ...PPG pin configuration Table 10 1 Pin Configuration Pin Name I O Function PO15 Output PO14 Output PO13 Output PO12 Output Group 3 pulse output PO11 Output PO10 Output PO9 Output PO8 Output Group 2 pul...

Page 414: ...RH Next data register L NDRL PPG output control register PCR PPG output mode register PMR 10 3 1 Next Data Enable Registers H L NDERH NDERL NDERH and NDERL enable disable pulse output on a bit by bit...

Page 415: ...he corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger Values are not transferred from NDRH to PODRH for cleared bits NDERL Bit Bit Name Initial Value R W Description...

Page 416: ...Initial Value R W PODRL 7 POD7 0 R W 6 POD6 0 R W 5 POD5 0 R W 4 POD4 0 R W 3 POD3 0 R W 2 POD2 0 R W 1 POD2 0 R W 0 POD0 0 R W Bit Bit Name Initial Value R W PODRH Bit Bit Name Initial Value R W Desc...

Page 417: ...is set to 1 the CPU cannot write to this register While NDERL is cleared the initial output value of the pulse can be set 10 3 3 Next Data Registers H L NDRH NDRL NDRH and NDRL store the next data for...

Page 418: ...groups 2 and 3 have different output triggers the upper four bits and lower four bits are mapped to different addresses as shown below Bit Bit Name Initial Value R W Description 7 6 5 4 NDR15 NDR14 ND...

Page 419: ...groups 0 and 1 have different output triggers the upper four bits and lower four bits are mapped to different addresses as shown below Bit Bit Name Initial Value R W Description 7 6 5 4 NDR7 NDR6 NDR...

Page 420: ...TPU channel 1 10 Compare match in TPU channel 2 11 Compare match in TPU channel 3 5 4 G2CMS1 G2CMS0 1 1 R W R W Group 2 Compare Match Select 1 and 0 These bits select output trigger of pulse output gr...

Page 421: ...ut 7 G3INV 1 R W 6 G2INV 1 R W 5 G1INV 1 R W 4 G0INV 1 R W 3 G3NOV 0 R W 2 G2NOV 0 R W 1 G1NOV 0 R W 0 G0NOV 0 R W Bit Bit Name Initial Value R W Bit Bit Name Initial Value R W Description 7 G3INV 1 R...

Page 422: ...utput values updated at compare match A in the selected TPU channel 1 Non overlapping operation output values updated at compare match A or B in the selected TPU channel 1 G1NOV 0 R W Group 1 Non Over...

Page 423: ...utput of data of up to 16 bits is possible by writing new output data to NDR before the next compare match Output trigger signal Pulse output pin Internal data bus Normal output inverted output C PODR...

Page 424: ...tch 1 Set TIOR to make TGRA an output compare register with output disabled 2 Set the PPG output trigger cycle 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clea...

Page 425: ...le of 5 Phase Pulse Output Figure 10 5 shows an example in which pulse output is used for cyclic 5 phase pulse output TCNT value TCNT TGRA H 0000 NDRH 00 80 C0 40 60 20 30 10 18 08 88 PODRH PO15 PO14...

Page 426: ...rrupt handling routine writes the next output data H C0 in NDRH 4 5 phase pulse output one or two phases active at a time can be obtained subsequently by writing H 40 H 60 H 20 H 30 H 10 H 18 H 08 H 8...

Page 427: ...his can be accomplished by having the TGIA interrupt handling routine write the next data in NDR or by having the TGIA interrupt activate the DTC Note however that the next data must be written before...

Page 428: ...put compare registers with output disabled 2 Set the pulse output trigger cycle in TGRB and the non overlapping margin in TGRA 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select...

Page 429: ...Non Overlapping Pulse Output Figure 10 9 shows an example in which pulse output is used for 4 phase complementary non overlapping pulse output TCNT value TCNT TGRB TGRA H 0000 NDRH 95 65 59 56 95 65 0...

Page 430: ...in the previous step to be the output trigger Set bits G3NOV and G2NOV in PMR to 1 to select non overlapping pulse output Write output data H 95 to NDRH 3 The timer counter in the TPU channel starts...

Page 431: ...eared to 0 values that are the inverse of the PODR contents can be output Figure 10 10 shows the outputs when the G3INV and G2INV bits are cleared to 0 in addition to the settings of figure 10 9 TCNT...

Page 432: ...10 5 Usage Notes 10 5 1 Module Stop State Setting PPG operation can be disabled or enabled using the module stop control register The initial value is for PPG operation to be halted Register access is...

Page 433: ...s The counters can be driven by one of six internal clock signals P 2 P 18 P 32 P 164 P 1024 or P 8192 or an external clock input Selection of three ways to clear the counters The counters can be clea...

Page 434: ...omparator A_1 TCORA_0 TCORB_0 TCSR_0 TCCR_0 TCORA_1 TCNT_1 TCORB_1 TCSR_1 TCCR_1 TCR_0 TCR_1 TCNT_0 Comparator B_0 Comparator B_1 A D conversion start request signal Internal bus Time constant registe...

Page 435: ...omparator A_3 TCORA_2 TCORB_2 TCSR_2 TCCR_2 TCORA_3 TCNT_3 TCORB_3 TCSR_3 TCCR_3 TCR_2 TCR_3 TCNT_2 Comparator B_2 Comparator B_3 A D conversion start request signal Internal bus Time constant registe...

Page 436: ...ernal reset to counter 1 Timer output pin TMO1 Output Outputs compare match Timer clock input pin TMCI1 Input Inputs external clock for counter Timer reset input pin TMRI1 Input Inputs external reset...

Page 437: ...stant register A_1 TCORA_1 Time constant register B_1 TCORB_1 Timer control register_1 TCR_1 Timer counter control register_1 TCCR_1 Timer control status register_1 TCSR_1 Unit 1 Channel 2 Timer count...

Page 438: ...0 R W 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 2 0 R W 1 0 R W 0 0 R W TCNT_0 TCNT_1 Bit Bit Name Initial Value R W 11 3 2 Time Constant Register A TCORA TCORA is an 8 bit readable writable register TC...

Page 439: ...ttings of bits OS3 and OS2 in TCSR TCORB is initialized to H FF 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 2 1 R W 1 1 R W 0 1 R W 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 2 1 R W 1 1 R W 0 1 R W TCORB_0...

Page 440: ...interrupt requests OVI are disabled 1 OVF interrupt requests OVI are enabled 4 3 CCLR1 CCLR0 0 0 R W R W Counter Clear 1 and 0 These bits select the method by which TCNT is cleared 00 Clearing is dis...

Page 441: ...W Description 7 to 4 0 R W Reserved These bits are always read as 0 The write value should always be 0 3 TMRIS 0 R W Timer Reset Input Select Selects an external reset input when the CCLR1 and CCLR0 b...

Page 442: ...1 Uses internal clock Counts at rising edge of P 1024 1 0 Uses internal clock Counts at falling edge of P 8192 1 1 Uses internal clock Counts at falling edge of P 1024 1 0 0 Counts at TCNT_1 overflow...

Page 443: ...match signal no incrementing clock is generated Do not use this setting 2 To use the external clock the DDR and ICR bits in the corresponding pin should be set to 0 and 1 respectively For details see...

Page 444: ...When writing 0 after reading CMFA 1 When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled be sure to read the flag after writing 0 to it When the DTC is act...

Page 445: ...change when compare match A occurs 01 0 is output when compare match A occurs 10 1 is output when compare match A occurs 11 Output is inverted when compare match A occurs toggle output Notes 1 Only 0...

Page 446: ...ure to read the flag after writing 0 to it 4 1 R Reserved This is a read only bit and cannot be modified 3 2 OS3 OS2 0 0 R W R W Output Select 3 and 2 2 These bits select a method of TMO pin output wh...

Page 447: ...that TCNT is cleared at a TCORA compare match 2 In TCSR set bits OS3 to OS0 to B 0110 causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match With these settings t...

Page 448: ...and CCLR0 in TCR to 1 and set the TMRIS bit in TCCR to 1 so that TCNT is cleared at the high level input of the TMRI signal 2 In TCSR set bits OS3 to OS0 to B 0110 causing the output to change to 1 a...

Page 449: ...ues P Internal clock TCNT input clock TCNT N 1 N N 1 Figure 11 5 Count Timing for Internal Clock Input at Falling Edge P External clock input pin TCNT input clock TCNT N 1 N N 1 Figure 11 6 Count Timi...

Page 450: ...its OS3 to OS0 in TCSR Figure 11 8 shows the timing when the timer output is toggled by the compare match A signal P Compare match A signal Timer output pin Figure 11 8 Timing of Toggled Timer Output...

Page 451: ...11 11 show the timing of this operation P Clear signal External reset input pin TCNT N H 00 N 1 Figure 11 10 Timing of Clearance by External Reset Rising Edge P Clear signal External reset input pin T...

Page 452: ...ter Clear Specification If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match the 16 bit counter TCNT_0 and TCNT_1 together is cleared when a 16 bit compare match event...

Page 453: ...es Name Interrupt Source Interrupt Flag DTC Activation Priority CMIA0 TCORA_0 compare match CMFA Possible VNUM 2 b00 High CMIB0 TCORB_0 compare match CMFB Possible VNUM 2 b01 OVI0 TCNT_0 overflow OVF...

Page 454: ...s last state Therefore the counter frequency is obtained by the following formula f N 1 f Counter frequency Operating frequency N TCOR value 11 8 2 Conflict between TCNT Write and Clear If a counter c...

Page 455: ...nput clock TCNT N M T1 T2 TCNT write cycle by CPU Counter write data Figure 11 14 Conflict between TCNT Write and Increment 11 8 4 Conflict between TCOR Write and Compare Match If a compare match even...

Page 456: ...d Table 11 5 shows the relationship between the timing at which the internal clock is switched by writing to bits CKS1 and CKS0 and the TCNT operation When the TCNT clock is generated from an internal...

Page 457: ...Clock after switchover TCNT input clock TCNT CKS bits changed N N 1 N 2 3 Switching from high to low 3 Clock before switchover Clock after switchover TCNT input clock TCNT CKS bits changed N N 1 N 2...

Page 458: ...ously 11 8 8 Module Stop State Setting Operation of the TMR can be disabled or enabled using the module stop control register The initial setting is for operation of the TMR to be halted Register acce...

Page 459: ...Selectable from eight counter input clocks Switchable between watchdog timer mode and interval timer mode In watchdog timer mode If the counter overflows the WDT outputs WDTOVF It is possible to selec...

Page 460: ...the following three registers To prevent accidental overwriting TCSR TCNT and RSTCSR have to be written to in a method different from normal registers For details see section 12 6 1 Notes on Register...

Page 461: ...o this bit to clear the flag Setting condition When TCNT overflows in interval timer mode changes from H FF to H 00 When internal reset request generation is selected in watchdog timer mode OVF is cle...

Page 462: ...read only bits and cannot be modified 2 1 0 CKS2 CKS1 CKS0 0 0 0 R W R W R W Clock Select 2 to 0 Select the clock source to be input to TCNT The overflow cycle for P 20 MHz is indicated in parenthese...

Page 463: ...low Flag This bit is set when TCNT overflows in watchdog timer mode This bit cannot be set in interval timer mode and only 0 can be written Setting condition When TCNT overflows changed from H FF to H...

Page 464: ...me time as the WDTOVF signal If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow the RES pin reset has priority and the WOVF bit in RSTCSR is...

Page 465: ...NT WT IT 1 TME 1 H 00 written to TCNT 133 states 2 519 states WDTOVF signal Internal reset signal 1 Notes 1 If TCNT overflows when the RSTE bit is set to 1 an internal reset signal is generated 2 130...

Page 466: ...rupt WOVI is requested at the same time the OVF bit in the TCSR is set to 1 TCNT value H 00 Time H FF WT IT 0 TME 1 WOVI Overflow Overflow Overflow Overflow WOVI Interval timer interrupt request WOVI...

Page 467: ...te to RSTCSR execute a word transfer instruction for address H FFA6 A byte transfer instruction cannot be used to write to RSTCSR The method of writing 0 to the WOVF bit in RSTCSR differs from that of...

Page 468: ...1 T2 Address P Internal write signal TCNT input clock TCNT TCNT write cycle Counter write data Figure 12 5 Conflict between TCNT Write and Increment 12 6 3 Changing Values of Bits CKS2 to CKS0 If bits...

Page 469: ...e sure that the WDTOVF signal is not input logically to the RES pin To reset the entire system by means of the WDTOVF signal use a circuit like that shown in figure 12 6 Reset input Reset signal to en...

Page 470: ...Section 12 Watchdog Timer WDT Rev 2 00 Jun 28 2007 Page 448 of 666 REJ09B0311 0200...

Page 471: ...chronous serial communication mode Full duplex communication capability The transmitter and receiver are mutually independent enabling transmission and reception to be executed simultaneously Double b...

Page 472: ...direct convention and inverse convention are supported RxD TxD SCK Clock P P 4 P 16 P 64 TEI TXI RXI ERI SCMR SSR SCR SMR Transmission reception control Baud rate generator BRR Module data bus RDR TS...

Page 473: ...xD0 Output Channel 0 transmit data output SCK1 I O Channel 1 clock input output RxD1 Input Channel 1 receive data input 1 TxD1 Output Channel 1 transmit data output SCK2 I O Channel 2 clock input outp...

Page 474: ...for each mode in the corresponding register sections Channel 0 Receive shift register_0 RSR_0 Transmit shift register_0 TSR_0 Receive data register_0 RDR_0 Transmit data register_0 TDR_0 Serial mode r...

Page 475: ...2 Serial control register_2 SCR_2 Serial status register_2 SSR_2 Smart card mode register_2 SCMR_2 Bit rate register_2 BRR_2 Serial extended mode register_2 SEMR_2 SCI_2 only Channel 4 Receive shift r...

Page 476: ...er confirming that the RDRF bit in SSR is set to 1 read RDR only once RDR cannot be written to by the CPU Bit Bit Name Initial Value R W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R 13 3 3 Transmit...

Page 477: ...e mode When SMIF in SCMR 0 7 C A 0 R W 6 CHR 0 R W 5 PE 0 R W 4 O E 0 R W 3 STOP 0 R W 2 MP 0 R W 1 CKS1 0 R W 0 CKS0 0 R W Bit Bit Name Initial Value R W When SMIF in SCMR 1 7 GM 0 R W 6 BLK 0 R W 5...

Page 478: ...y in asynchronous mode Selects the stop bit length in transmission 0 1 stop bit 1 2 stop bits In reception only the first stop bit is checked If the second stop bit is 0 it is treated as the start bit...

Page 479: ...le valid only in asynchronous mode When this bit is set to 1 the parity bit is added to transmit data before transmission and the parity bit is checked in reception Set this bit to 1 in smart card int...

Page 480: ...t Rate Register BRR Note etu Elementary Time Unit 1 bit transfer time 13 3 6 Serial Control Register SCR SCR is a register that enables disables the following SCI transfer operations and interrupt req...

Page 481: ...r by clearing the RIE bit to 0 5 TE 0 R W Transmit Enable When this bit is set to 1 transmission is enabled Under this condition serial transmission is started by writing transmit data to TDR and clea...

Page 482: ...ommunication Function When receive data including MPB 0 in SSR is being received transfer of the received data from RSR to RDR detection of reception errors and the settings of RDRF FER and ORER flags...

Page 483: ...mode 0X Internal clock SCK pin functions as clock output 1X External clock SCK pin functions as clock input Note X Don t care Bit Functions in Smart Card Interface Mode When SMIF in SCMR 1 Bit Bit Nam...

Page 484: ...nous clock input in clocked synchronous mode Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format Even if reception is halted by clearing this bit to...

Page 485: ...SCMR 1 Bit Bit Name Initial Value R W 7 TDRE 1 R W 6 RDRF 0 R W 5 ORER 0 R W 4 ERS 0 R W 3 PER 0 R W 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R W Note Only 0 can be written to clear the flag Bit Functions in Nor...

Page 486: ...en the next serial reception is completed while the RDRF flag is being set to 1 an overrun error occurs and the received data is lost 5 ORER 0 R W Overrun Error Indicates that an overrun error has occ...

Page 487: ...clear this flag by writing 0 while the corresponding interrupt is enabled be sure to read the flag after writing 0 to it Even when the RE bit in SCR is cleared the FER flag is not affected and retain...

Page 488: ...s previous state is retained 0 MPBT 0 R W Multiprocessor Bit Transfer Sets the multiprocessor bit value to be added to the transmit frame Note Only 0 can be written to clear the flag Bit Functions in...

Page 489: ...when the next reception is completed while the RDRF flag is being set to 1 an overrun error occurs and the received data is lost 5 ORER 0 R W Overrun Error Indicates that an overrun error has occurred...

Page 490: ...ing condition When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR however the RDRF flag is not set Note that when the PER flag is being set...

Page 491: ...yte data transfer The set timing depends on the register setting as follows When GM 0 and BLK 0 2 5 etu after transmission start When GM 0 and BLK 1 1 5 etu after transmission start When GM 1 and BLK...

Page 492: ...when the 8 bit data format is used for transmission reception when the 7 bit data format is used data is always transmitted received with LSB first 2 SINV 0 R W Smart Card Data Invert Inverts the tra...

Page 493: ...Clocked synchronous mode N 1 8 2 B 2n 1 P 106 Smart card interface mode N 1 S 2 B P 106 2n 1 Error B S 2 N 1 1 100 2n 1 P 106 Legend B Bit rate bit s N BRR setting for baud rate generator 0 N 255 P O...

Page 494: ...64 0 16 0 77 0 16 9600 0 25 0 16 0 31 0 00 0 32 1 36 0 38 0 16 19200 0 12 0 16 0 15 0 00 0 15 1 73 0 19 2 34 31250 0 7 0 00 0 9 1 70 0 9 0 00 0 11 0 00 38400 0 7 0 00 0 7 1 73 0 9 2 34 Operating Frequ...

Page 495: ...0 129 0 16 9600 0 55 0 00 0 58 0 69 0 63 0 00 0 64 0 16 19200 0 27 0 00 0 28 1 02 0 31 0 00 0 32 1 36 31250 0 16 1 20 0 17 0 00 0 19 1 70 0 19 0 00 38400 0 13 0 00 0 14 2 34 0 15 0 00 0 15 1 73 Opera...

Page 496: ...for Each Operating Frequency Asynchronous Mode P MHz Maximum Bit Rate bit s n N 8 250000 0 0 9 8304 307200 0 0 10 312500 0 0 12 375000 0 0 12 288 384000 0 0 14 437500 0 0 14 7456 460800 0 0 16 500000...

Page 497: ...ronous Mode P MHz External Input Clock MHz Maximum Bit Rate bit s 8 2 0000 125000 9 8304 2 4576 153600 10 2 5000 156250 12 3 0000 187500 12 288 3 0720 192000 14 3 5000 218750 14 7456 3 6864 230400 16...

Page 498: ...us Mode Operating Frequency P MHz 8 10 16 20 Bit Rate bit s n N n N n N n N 110 250 3 124 3 249 500 2 249 3 124 1k 2 124 2 249 2 5k 1 199 1 249 2 99 2 124 5k 1 99 1 124 1 199 1 249 10k 0 199 0 249 1 9...

Page 499: ...0k 0 24 0 29 0 32 0 34 500k 0 14 1M 2 5M 0 2 5M Legend Space Setting prohibited Can be set but there will be error Continuous transmission or reception is not possible Table 13 7 Maximum Bit Rate with...

Page 500: ...bit s n N Error n N Error n N Error n N Error 9600 0 1 0 00 0 1 12 01 0 2 15 99 0 2 6 60 Operating Frequency P MHz 25 00 30 00 33 00 35 00 Bit Rate bit s n N Error n N Error n N Error n N Error 9600 0...

Page 501: ...it Name Initial Value R W 3 ABCS 0 R W 2 ACS2 0 R W 1 ACS1 0 R W 0 ACS0 0 R W Bit Bit Name Initial Value R W Description 7 0 R W Reserved This bit is always read as 0 The write value should always be...

Page 502: ...kbps of average transfer rate specific to P 10 667 MHz is selected operated using the basic clock with a frequency 8 times the transfer rate 011 720 kbps of average transfer rate specific to P 32 MHz...

Page 503: ...the space state low level recognizes a start bit and starts serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the transmitt...

Page 504: ...13 10 Serial Transfer Formats Asynchronous Mode PE 0 0 1 1 0 0 1 1 S 8 bit data STOP S 7 bit data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit dat...

Page 505: ...n in figure 13 3 Thus the reception margin in asynchronous mode is determined by formula 1 below M 0 5 L 0 5 F 1 F 100 Formula 1 2N 1 N D 0 5 M Reception margin N Ratio of bit rate to clock N 16 D Dut...

Page 506: ...CKE0 bits in SCR When an external clock is input to the SCK pin the clock frequency should be 16 times the bit rate used When the SCI is operated on an internal clock the clock can be output from the...

Page 507: ...t in SMR and SCMR 2 Set CKE1 and CKE0 bits in SCR TE and RE bits are 0 No Yes Set value in BRR Set corresponding bit in ICR to 1 3 4 Set TE or RE bit in SCR to 1 and set RIE TIE TEIE and MPIE bits 5 1...

Page 508: ...t transmit data parity bit or multiprocessor bit may be omitted depending on the format and stop bit 4 The SCI checks the TDRE flag at the timing for sending the stop bit 5 If the TDRE flag is 0 the n...

Page 509: ...enabled 2 SCI state check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation proc...

Page 510: ...R If the RIE bit in SCR is set to 1 at this time an ERI interrupt request is generated 4 If a framing error when the stop bit is 0 is detected the FER bit in SSR is set to 1 and receive data is transf...

Page 511: ...ER and RDRF bits to 0 before resuming reception Figure 13 9 shows a sample flowchart for serial data reception Table 13 11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF ORER FER PER...

Page 512: ...ropriate error processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detec...

Page 513: ...6 REJ09B0311 0200 End 3 Error processing Parity error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Bre...

Page 514: ...nds data which includes the ID code of the receiving station and a multiprocessor bit set to 1 It then transmits transmit data added with a multiprocessor bit cleared to 0 The receiving station skips...

Page 515: ...C Receiving station D ID 01 ID 02 ID 03 ID 04 Communication line Serial data ID transmission cycle receiving station specification Data transmission cycle Data transmission to receiving station speci...

Page 516: ...itialization The TxD pin is automatically designated as the transmit data output pin After the TE bit is set to 1 a 1 is output for one frame and transmission is enabled 2 SCI status check and transmi...

Page 517: ...MPB Stop bit Data ID2 Start bit Stop bit Start bit Data Data 2 Stop bit RXI interrupt request multiprocessor interrupt generated Idle state mark state RDRF RDR data read and RDRF flag cleared to 0 in...

Page 518: ...D reception and comparison Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE b...

Page 519: ...497 of 666 REJ09B0311 0200 End Error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR...

Page 520: ...receiver also have a double buffered structure so that the next transmit data can be written during transmission or the previous receive data can be read during reception enabling continuous data tra...

Page 521: ...t in ICR to 1 2 3 Set TE or RE bit in SCR to 1 and set RIE TIE TEIE and MPIE bits 5 1 bit interval elapsed Set CKE1 and CKE0 bits in SCR TE and RE bits are 0 1 1 Set the bit in ICR for the correspondi...

Page 522: ...e enabled 3 8 bit data is sent from the TxD pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has bee...

Page 523: ...TDRE flag in SSR to 0 No Yes No Yes Read TEND flag in SSR 3 Clear TE bit in SCR to 0 TDRE 1 All data transmitted TEND 1 1 SCI initialization The TxD pin is automatically designated as the transmit dat...

Page 524: ...s to be set to 1 3 If reception finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request is...

Page 525: ...the ORER flag in SSR and after performing the appropriate error processing clear the ORER flag to 0 Receive cannot be resumed if the ORER flag is set to 1 4 SCI state check and receive data read Read...

Page 526: ...operations To switch from transmit mode to simultaneous transmit and receive mode after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1 clear the TE bit to 0...

Page 527: ...ption cannot be resumed if the ORER flag is set to 1 4 SCI state check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag...

Page 528: ...As in the figure since this LSI communicates with the IC card using a single transmission line interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor Setting...

Page 529: ...1 etu after 10 5 etu has passed from the start bit If an error signal is sampled during transmission the same data is automatically re transmitted after at least 2 etu Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp In...

Page 530: ...se convention type write 1 to both the SDIR and SINV bits in SCMR The parity bit is logic level 0 to produce even parity which is prescribed by the smart card standard and corresponds to state Z Since...

Page 531: ...data is sampled on the 16th 32nd 186th and 128th rising edges of the basic clock so that it can be latched at the middle of each bit as shown in figure 13 25 The reception margin here is determined by...

Page 532: ...ance state 6 Set the value corresponding to the bit rate in BRR 7 Set the CKE1 and CKE0 bits in SCR appropriately Clear the TIE RIE TE RE MPIE and TEIE bits to 0 simultaneously When the CKE0 bit is se...

Page 533: ...request is generated if the TIE bit in SCR is set to 1 Writing transmit data to TDR starts transmission of the next data Figure 13 28 shows a sample flowchart for transmission All the processing step...

Page 534: ...TSR Transfer from TDR to TSR Transfer from TDR to TSR 2 4 3 Figure 13 26 Data Re Transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit...

Page 535: ...B0311 0200 Initialization No Yes Clear TE bit in SCR to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing T...

Page 536: ...rmed using an RXI interrupt request to activate the DTC In reception setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1 This activates the DTC by a...

Page 537: ...0 RDRF 1 All data received Yes Figure 13 30 Sample Reception Flowchart 13 7 8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1 Spe...

Page 538: ...oftware standby mode 1 Set the data register DR and data direction register DDR corresponding to the SCK pin to the values for the output fixed state in software standby mode 2 Write 0 to the TE and R...

Page 539: ...flag in SSR is set to 1 an RXI interrupt request is generated When the ORER PER or FER flag in SSR is set to 1 an ERI interrupt request is generated An RXI interrupt can activate the DTC to allow data...

Page 540: ...If an error occurs the SCI automatically re transmits the same data During re transmission the TEND flag remains as 0 thus not activating the DTC Therefore the SCI and DTC automatically transmit the s...

Page 541: ...used as an I O port whose direction input or output and level are determined by DR and DDR This can be used to set the TxD pin to mark state high level or send a break during serial data transmission...

Page 542: ...us data in TDR is lost Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1 13 9 6 Restrictions on Using DTC When the external clock source is used as a synchronization...

Page 543: ...the SCI first Figure 13 34 shows a sample flowchart for transition to software standby mode during transmission Figures 13 35 and 13 36 show the port pin states during transition to software standby...

Page 544: ...are standby mode however if the DTC has been activated the data remaining in the DTC will be transmitted when both the TE and TIE bits are set to 1 2 Clear the TIE and TEIE bits to 0 when they are 1 3...

Page 545: ...TxD bit retained Note Initialized in software standby mode Figure 13 36 Port Pin States during Transition to Software Standby Mode Internal Clock Clocked Synchronous Transmission Start reception Recep...

Page 546: ...Section 13 Serial Communication Interface SCI Rev 2 00 Jun 28 2007 Page 524 of 666 REJ09B0311 0200...

Page 547: ...el at 35 MHz operation Two kinds of operating modes Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels or 1 to 8 channels Eight data registers A D convers...

Page 548: ...nversion start trigger from the TPU or TMR Successive approximation register Multiplexer Legend ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data reg...

Page 549: ...alog input pin 7 AN7 Input A D external trigger input pin ADTRG0 Input External trigger input for starting A D conversion Analog power supply pin AVCC Input Analog block power supply Analog ground pin...

Page 550: ...e lower 6 bit data is always read as 0 The data bus between the CPU and the A D converter has a 16 bit width The data can be read directly from the CPU ADDR must not be accessed in 8 bit units and mus...

Page 551: ...en 0 is written after reading ADF 1 When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled be sure to read the flag after writing 0 to it When the DTC is act...

Page 552: ...AN1 0010 AN2 0011 AN3 0100 AN4 0101 AN5 0110 AN6 0111 AN7 1XXX Setting prohibited When SCANE 1 and SCANS 0 0000 AN0 0001 AN0 and AN1 0010 AN0 to AN2 0011 AN0 to AN3 0100 AN4 0101 AN4 and AN5 0110 AN4...

Page 553: ...isabled 01 A D conversion start by external trigger from TPU is enabled 10 A D conversion start by external trigger from TMR is enabled 11 A D conversion start by the ADTRG0 pin is enabled 5 4 SCANE S...

Page 554: ...t can be set to 1 at the same time as the operating mode or analog input channel is changed 14 4 1 Single Mode In single mode A D conversion is to be performed only once on the analog input of the spe...

Page 555: ...er Operation Single Mode Channel 1 Selected 14 4 2 Scan Mode In scan mode A D conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight channels 1 W...

Page 556: ...ADST ADF ADDRA ADDRB ADDRC ADDRD Set 1 Clear 1 Clear 1 2 Waiting for conversion Channel 0 AN0 operation state Channel 1 AN1 operation state Channel 2 AN2 operation state Channel 3 AN3 operation state...

Page 557: ...pling time tSPL The length of tD varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in table 14 3 In scan mode the value...

Page 558: ...Typ Max Min Typ Max Min Typ Max Min Typ Ma x A D conversion start delay time tD 18 33 10 17 6 9 4 5 Input sampling time tSPL 127 63 31 15 A D conversion time tCONV 515 530 259 266 131 134 67 68 Note V...

Page 559: ...ng P ADTRG0 Internal trigger signal ADST A D conversion Figure 14 5 External Trigger Input Timing 14 5 Interrupt Source The A D converter generates an A D conversion end interrupt ADI at the end of A...

Page 560: ...he minimum voltage value B 0000000000 H 000 to B 0000000001 H 001 see figure 14 7 Full scale error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the...

Page 561: ...Quantization error Digital output Ideal A D conversion characteristic Analog input voltage Figure 14 6 A D Conversion Accuracy Definitions FS Digital output Ideal A D conversion characteristic Nonline...

Page 562: ...tance to be charged within the sampling time if the sensor output impedance exceeds 10 k charging may be insufficient and it may not be possible to guarantee the A D conversion accuracy However if a l...

Page 563: ...tween AVcc AVss and Vcc Vss As the relationship between AVcc AVss and Vcc Vss set AVcc Vcc 0 3 V and AVss Vss If the A D converter is not used set AVcc Vcc and AVss Vss Vref setting range The referenc...

Page 564: ...N0 to AN7 pins are averaged and so an error may arise Also when A D conversion is performed frequently as in scan mode if the current charged and discharged by the capacitance of the sample and hold c...

Page 565: ...Circuit 14 7 7 A D Input Hold Function in Software Standby Mode When this LSI enters software standby mode with A D conversion enabled the analog inputs are retained and the analog power supply curre...

Page 566: ...Section 14 A D Converter Rev 2 00 Jun 28 2007 Page 544 of 666 REJ09B0311 0200...

Page 567: ...10 s with 20 pF load Output voltage of 0 V to Vref D A output hold function in software standby mode Module stop state specifiable Module data bus Internal data bus Vref AVCC DA1 DA0 AVSS 8 bit D A C...

Page 568: ...t pin 0 DA0 Output Channel 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output 15 3 Register Descriptions The D A converter has the following registers D A data register 0 DADR0 D A...

Page 569: ...1 DA1 is enabled 6 DAOE0 0 R W D A Output Enable 0 Controls D A conversion and analog output 0 Analog output of channel 0 DA0 is disabled 1 D A conversion of channel 0 is enabled Analog output of cha...

Page 570: ...f channel 0 DA0 is disabled and analog output of channel 1 DA1 is enabled 1 D A conversion of channels 0 and 1 is enabled Analog output of channels 0 and 1 DA0 and DA1 is enabled 1 0 0 D A conversion...

Page 571: ...nalog output pin DA0 after the conversion time tDCONV has elapsed The conversion result continues to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0 The output value is expr...

Page 572: ...lted Register access is enabled by clearing the module stop state For details see section 18 Power Down States 15 5 2 D A Output Hold Function in Software Standby Mode When this LSI enters software st...

Page 573: ...32 bit data bus enabling one state access by the CPU to all byte data word data and longword data The on chip RAM can be enabled or disabled by means of the RAME bit in the system control register SY...

Page 574: ...Section 16 RAM Rev 2 00 Jun 28 2007 Page 552 of 666 REJ09B0311 0200...

Page 575: ...clock frequencies This LSI supports three types of clocks a system clock provided to the CPU and bus masters a peripheral module clock provided to the peripheral modules and an external bus clock pro...

Page 576: ...module and external bus clocks Bit Bit Name Initial Value R W 15 PSTOP1 0 R W 14 0 R W 13 0 R W 12 0 R W 11 0 R W 10 ICK2 0 R W 9 ICK1 1 R W 8 ICK0 0 R W Bit Bit Name Initial Value R W 7 0 R W 6 PCK2...

Page 577: ...system clock is lower than that of the two clocks 7 0 R W Reserved This bit is always read as 0 The write value should always be 0 6 5 4 PCK2 PCK1 PCK0 0 1 0 R W R W R W Peripheral Module Clock P Sele...

Page 578: ...ct the frequency of the external bus clock The ratio to the input clock is as follows 000 4 001 2 010 1 011 1 2 1XX Setting prohibited The frequency of the external bus clock should be lower than that...

Page 579: ...parallel resonance type should be used When the clock is provided by connecting a crystal resonator a crystal resonator having a frequency of 8 to 18 MHz should be connected EXTAL XTAL Rd CL2 CL1 CL1...

Page 580: ...nput b Counter clock input on XTAL pin Figure 17 4 External Clock Input Examples For the input conditions of the external clock refer to table 20 4 Clock Timing in section 20 3 1 Clock Timing The inpu...

Page 581: ...operate on the P Therefore note that the time processing of modules such as a timer and SCI differs before and after changing the clock division ratio In addition wait time for clearing software stan...

Page 582: ...circuit parameters for the resonator will depend on the floating capacitance of the resonator and the mounting circuit the parameters should be determined in consultation with the resonator manufactur...

Page 583: ...for the PLL circuit Separate PLLVcc and PLLVss from the other Vcc and Vss lines at the board power supply source and be sure to insert bypass capacitors CPB and CB close to the pins PLLVCC PLLVSS VCC...

Page 584: ...Section 17 Clock Pulse Generator Rev 2 00 Jun 28 2007 Page 562 of 666 REJ09B0311 0200...

Page 585: ...p function The functions for each peripheral module can be stopped to make a transition to the power down state Transition function to power down state Transition to the power down state is possible t...

Page 586: ...timer Functions Functions Halted retained Halted 8 bit timer Functions Functions 4 Halted retained Halted Other peripheral modules Functions Halted 1 Halted 1 Halted 3 I O port Functions Retained Ret...

Page 587: ...ared to 0 2 NMI and IRQ0 to IRQ11 Note that IRQ is valid only when the corresponding bit in SSIER is set to 1 From any state a transition to hardware standby mode occurs when STBY is driven low From a...

Page 588: ...er the SLEEP instruction is executed This bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation For clearing write 0 to this bit Whe...

Page 589: ...standby time is at least equal to the oscillation settling time With an external clock a PLL circuit settling time is necessary Refer to table 18 2 to set the standby time While oscillation is being...

Page 590: ...nstruction exception handling or causes a transition to the power down state 0 The execution of a SLEEP instruction causes a transition to the power down state 1 The execution of a SLEEP instruction i...

Page 591: ...MSTPA14 0 R W 13 MSTPA13 0 R W 12 MSTPA12 0 R W 11 MSTPA11 1 R W 10 MSTPA10 1 R W 9 MSTPA9 1 R W 8 MSTPA8 1 R W Bit Bit Name Initial Value R W 7 MSTPA7 1 R W 6 MSTPA6 1 R W 5 MSTPA5 1 R W 4 MSTPA4 1...

Page 592: ...Reserved These bits are always read as 0 The write value should always be 0 12 MSTPA12 0 R W Data transfer controller DTC 11 10 MSTPA11 MSTPA10 1 1 R W R W Reserved These bits are always read as 1 Th...

Page 593: ...2 1 R W Serial communication interface_4 SCI_4 11 MSTPB11 1 R W Reserved This bit is always read as 1 The write value should always be 1 10 MSTPB10 1 R W Serial communication interface_2 SCI_2 9 MSTPB...

Page 594: ...R W 7 MSTPC7 0 R W 6 MSTPC6 0 R W 5 MSTPC5 0 R W 4 MSTPC4 0 R W 3 MSTPC3 0 R W 2 MSTPC2 0 R W 1 MSTPC1 0 R W 0 MSTPC0 0 R W Bit Bit Name Initial Value R W Module 15 14 13 12 11 10 9 8 MSTPC15 MSTPC14...

Page 595: ...ternal bus clocks The peripheral module and external bus clocks are restricted to the operating clock specified by bits ICK2 to ICK0 18 4 Module Stop Function Module stop function can be set for indiv...

Page 596: ...y a watchdog timer overflow 1 Clearing by interrupt When an interrupt occurs sleep mode is exited and interrupt exception processing starts Sleep mode is not exited if the interrupt is disabled or int...

Page 597: ...han NMI are masked on the CPU side or if the relevant interrupt is designated as a DTC activation source When the STBY pin is driven low a transition is made to hardware standby mode Note Operation or...

Page 598: ...or has been designated as a DTC activation source Note By setting the SSIn bit in SSIER to 1 IRQ0 to IRQ11 can be used as a software standby mode clearing source 2 Clearing by RES pin When the RES pi...

Page 599: ...1 8 2 6 3 2 1 0 512 14 6 20 5 25 6 1 1024 29 3 41 0 51 2 1 0 0 0 2048 58 5 81 9 102 4 1 4096 0 12 0 16 0 20 ms 1 0 16384 0 47 0 66 0 82 1 32768 0 94 1 31 1 64 1 0 0 65536 1 87 2 62 3 28 1 131072 3 74...

Page 600: ...51 2 64 0 1 1024 78 8 102 4 128 0 1 0 0 0 2048 157 5 204 8 256 0 1 4096 0 32 0 41 0 51 ms 1 0 16384 1 26 1 64 2 05 1 32765 2 52 3 28 4 10 1 0 0 65536 5 04 6 55 8 19 1 131072 10 08 13 11 16 38 1 0 2621...

Page 601: ...upt is accepted with the NMIEG bit in INTCR cleared to 0 falling edge specification then the NMIEG bit is set to 1 rising edge specification the SSBY bit is set to 1 and a SLEEP instruction is execute...

Page 602: ...by Mode Hardware standby mode is cleared by means of the STBY pin and the RES pin When the STBY pin is driven high while the RES pin is low the reset state is entered and clock oscillation is started...

Page 603: ...driven low with the STBY pin driven high for a given time in order to clear the reset state To enter hardware standby mode immediately after power on drive the STBY pin low after exiting the reset sta...

Page 604: ...to 0 a transition is made to the power down state The power down state is canceled by a canceling factor interrupt see figure 18 5 When a canceling factor interrupt is generated immediately before th...

Page 605: ...ction Execution SLPIE 0 Power down state RTE instruction executed Return from the power down state after the next canceling factor interrupt is generated Transition by exception handling No Yes Cancel...

Page 606: ...ceotion handling Instruction before SLEEP instruction SLEEP instruction executed SLPIE 1 Instruction after SLEEP instruction Exception servise routine RTE instruction executed Transition by exception...

Page 607: ...When DDR for the PA7 pin is cleared to 0 the B clock output is disabled and the pin becomes an input port Tables 18 3 shows the states of the B pin in each processing state Table 18 3 B Pin PA7 State...

Page 608: ...perating state of the DTC bit MSTPA12 may not be set to 1 Setting of the DTC module stop state should be carried out only when the DTC is not activated For details see section 7 Data Transfer Controll...

Page 609: ...addresses otherwise the operation when accessing these bits and subsequent operations cannot be guaranteed 2 Register bits Bit configurations of the registers are listed in the same order as the regi...

Page 610: ...ontrol register P2ICR 8 H FFB91 I O port 8 2P 2P Port 3 input buffer control register P3ICR 8 H FFB92 I O port 8 2P 2P Port 5 input buffer control register P5ICR 8 H FFB94 I O port 8 2P 2P Port 6 inpu...

Page 611: ...function control register 4 PFCR4 8 H FFBC4 I O port 8 2P 3P Port function control register 6 PFCR6 8 H FFBC6 I O port 8 2P 3P Port function control register 9 PFCR9 8 H FFBC9 I O port 8 2P 3P Port fu...

Page 612: ...FD98 BSC 16 2I 3I Burst ROM interface control register BROMCR 16 H FFD9A BSC 16 2I 3I Address data multiplexed I O control register MPXCR 16 H FFD9C BSC 16 2I 3I Mode control register MDCR 16 H FFDC0...

Page 613: ...TMR_2 16 2P 2P Timer counter control register_3 TCCR_3 8 H FFECB TMR_3 16 2P 2P Timer control register_4 TCR_4 8 H FFEE0 TPU_4 16 2P 2P Timer mode register_4 TMDR_4 8 H FFEE1 TPU_4 16 2P 2P Timer I O...

Page 614: ...ol register INTCR 8 H FFF32 INTC 16 2I 3I CPU priority control register CPUPCR 8 H FFF33 INTC 16 2I 3I IRQ enable register IER 16 H FFF34 INTC 16 2I 3I IRQ status register ISR 16 H FFF36 INTC 16 2I 3I...

Page 615: ...SCI_2 8 2P 2P Serial status register_2 SSR_2 8 H FFF64 SCI_2 8 2P 2P Receive data register_2 RDR_2 8 H FFF65 SCI_2 8 2P 2P Smart card mode register_2 SCMR_2 8 H FFF66 SCI_2 8 2P 2P D A data register 0...

Page 616: ...egister_1 SSR_1 8 H FFF8C SCI_1 8 2P 2P Receive data register_1 RDR_1 8 H FFF8D SCI_1 8 2P 2P Smart card mode register_1 SCMR_1 8 H FFF8E SCI_1 8 2P 2P A D data register A ADDRA 16 H FFF90 A D 16 2P 2...

Page 617: ...2P 2P Timer mode register_0 TMDR_0 8 H FFFC1 TPU_0 16 2P 2P Timer I O control register H_0 TIORH_0 8 H FFFC2 TPU_0 16 2P 2P Timer I O control register L_0 TIORL_0 8 H FFFC3 TPU_0 16 2P 2P Timer interr...

Page 618: ...2P 2P Timer I O control register L_3 TIORL_3 8 H FFFF3 TPU_3 16 2P 2P Timer interrupt enable register_3 TIER_3 8 H FFFF4 TPU_3 16 2P 2P Timer status register_3 TSR_3 8 H FFFF5 TPU_3 16 2P 2P Timer co...

Page 619: ...PE1DDR PE0DDR PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR P1ICR P17ICR P16ICR P15ICR P14ICR P13ICR P12ICR P11ICR P10ICR P2ICR P27ICR P26ICR P25ICR P24ICR P23ICR P22ICR P21ICR P20ICR...

Page 620: ...S0E PFCR1 CS7SA CS7SB CS6SA CS6SB CS5SA CS5SB CS4SA CS4SB PFCR2 CS2S BSS BSE RDWRE ASOE PFCR4 A23E A22E A21E PFCR6 LHWROE TCLKS PFCR9 TPUMS5 TPUMS4 TPUMS3A TPUMS3B TPUMS2 TPUMS1 TPUMS0A TPUMS0B PFCRB...

Page 621: ...ABWL2 ABWL1 ABWL0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 ASTCR W72 W71 W70 W62 W61 W60 WTCRA W52 W51 W50 W42 W41 W40 W32 W31 W30 W22 W21 W20 WTCRB W12 W11 W10 W02 W01 W00 RDN7 RDN6 RDN5 RDN4 RDN3 RDN...

Page 622: ...PB8 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 MSTPC15 MSTPC14 MSTPC13 MSTPC12 MSTPC11 MSTPC10 MSTPC9 MSTPC8 MSTPCRC MSTPC7 MSTPC5 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 SEMR_2...

Page 623: ...FU TCFV TGFB TGFA TCNT_5 TGRA_5 TGRB_5 DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 INTC DTCERA DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9...

Page 624: ...34 P33 P32 P31 P30 PORT5 P57 P56 P55 P54 P53 P52 P51 P50 PORT6 P65 P64 P63 P62 P61 P60 PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTB PB3 PB2 PB1 PB0 PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PORTE PE7 PE6 P...

Page 625: ...R1 NDER0 PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 NDRH 2 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 NDRL 2 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR...

Page 626: ...0 TMR_0 TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_1 TCSR_0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 TMR_0 TCSR_1 CMFB CMFA OVF OS3 OS2 OS1 OS0 TMR_1 TCORA_0 TMR_0 TCORA_1 TMR_1 TCORB_0 TMR_0 TCO...

Page 627: ...A_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_1 TMDR_1 MD2 MD1 MD0 TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA TSR_1 TCFD TCFU TGF...

Page 628: ...FD TCFV TGFD TGFC TGFB TGFA TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 Notes 1 Parts of the bit functions differ in normal mode and the smart card interface 2 When the same output trigger is specified for pul...

Page 629: ...ized PBDDR Initialized Initialized PDDDR Initialized Initialized PEDDR Initialized Initialized PFDDR Initialized Initialized P1ICR Initialized Initialized P2ICR Initialized Initialized P3ICR Initializ...

Page 630: ...ialized Initialized PFCR0 Initialized Initialized PFCR1 Initialized Initialized PFCR2 Initialized Initialized PFCR4 Initialized Initialized PFCR6 Initialized Initialized PFCR9 Initialized Initialized...

Page 631: ...lized ENDIANCR Initialized Initialized SRAMCR Initialized Initialized BROMCR Initialized Initialized MPXCR Initialized Initialized MDCR Initialized Initialized SYSTEM SYSCR Initialized Initialized SCK...

Page 632: ...3 Initialized Initialized TMR_3 TCNT_2 Initialized Initialized TMR_2 TCNT_3 Initialized Initialized TMR_3 TCCR_2 Initialized Initialized TMR_2 TCCR_3 Initialized Initialized TMR_3 TCR_4 Initialized In...

Page 633: ...nitialized DTCERD Initialized Initialized DTCERE Initialized Initialized DTCERF Initialized Initialized DTCERG Initialized Initialized DTCERH Initialized Initialized DTCCR Initialized Initialized INTC...

Page 634: ...itialized Initialized RDR_2 Initialized Initialized Initialized Initialized Initialized SCMR_2 Initialized Initialized DADR0 Initialized Initialized D A DADR1 Initialized Initialized DACR01 Initialize...

Page 635: ...Initialized Initialized ADDRA Initialized Initialized A D ADDRB Initialized Initialized ADDRC Initialized Initialized ADDRD Initialized Initialized ADDRE Initialized Initialized ADDRF Initialized Init...

Page 636: ...ized Initialized TIORH_0 Initialized Initialized TIORL_0 Initialized Initialized TIER_0 Initialized Initialized TSR_0 Initialized Initialized TCNT_0 Initialized Initialized TGRA_0 Initialized Initiali...

Page 637: ...TPU_2 TCNT_2 Initialized Initialized TGRA_2 Initialized Initialized TGRB_2 Initialized Initialized TCR_3 Initialized Initialized TPU_3 TMDR_3 Initialized Initialized TIORH_3 Initialized Initialized T...

Page 638: ...Section 19 List of Registers Rev 2 00 Jun 28 2007 Page 616 of 666 REJ09B0311 0200...

Page 639: ...Input voltage except port 5 Vin 0 3 to VCC 0 3 V Input voltage port 5 Vin 0 3 to AVCC 0 3 V Reference power supply voltage Vref 0 3 to AVCC 0 3 V Analog power supply voltage AVCC 0 3 to 4 6 V Analog i...

Page 640: ...port 3 VT VT VCC 0 06 V Port 5 2 VT AVCC 0 2 V VT AVCC 0 7 V VT VT AVCC 0 06 V MD RES STBY EMLE NMI VIH VCC 0 9 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 V Other input pins VCC 0 7 VCC 0 3 V Input high voltage...

Page 641: ...I ITSI 1 0 A Vin 0 5 to VCC 0 5 V Input pull up MOS current Ports D to F H I Ip 10 300 A VCC 3 0 to 3 6 V Vin 0 V Input capacitance All input pins Cin 15 pF Vin 0 V f 1 MHz Ta 25 C Normal operation I...

Page 642: ...0 mA 0 27 mA MHz V VCC f sleep mode 6 The values are for reference 7 This can be applied when the RES pin is held low at power on Table 20 3 Permissible Output Currents Conditions VCC 3 0 V to 3 6 V A...

Page 643: ...istics Rev 2 00 Jun 28 2007 Page 621 of 666 REJ09B0311 0200 20 3 AC Characteristics LSI output pin C RH RL 3 V C 30 pF RL 2 4 k RH 12 k Input output timing measurement level 1 5 V Vcc 3 0 V to 3 6 V F...

Page 644: ...0 125 ns Figure 20 2 Clock high pulse width tCH 5 ns Clock low pulse width tCL 5 ns Clock rising time tCr 5 ns Clock falling time tCf 5 ns Oscillation settling time after reset crystal tOSC1 10 ms Fi...

Page 645: ...standby mode power down mode Oscillation settling time tOSC2 I NMI NMI exception handling NMIEG 1 SSBY 1 NMI exception handling SLEEP instruction NMIEG SSBY Figure 20 3 Oscillation Settling Timing af...

Page 646: ...MHz to 50 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 ns Figure 20 6 RES pulse width tRESW 2...

Page 647: ...3 6 V Vref 3 0 V to AVCC VSS AVSS 0 V B 8 MHz to 50 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Item Symbol Min Max Unit Test Conditions Address delay time tA...

Page 648: ...RDH1 0 ns Read data hold time 2 tRDH2 0 ns Read data access time 2 tAC2 1 5 tcyc 20 ns Read data access time 4 tAC4 2 5 tcyc 20 ns Read data access time 5 tAC5 1 0 tcyc 20 ns Read data access time 6 t...

Page 649: ...tcyc 8 ns Write data hold time 3 tWDH3 1 5 tcyc 8 ns Byte control delay time tUBD 15 ns Figures 20 13 20 14 Byte control pulse width 1 tUBW1 1 0 tcyc 15 ns Figure 20 13 Byte control pulse width 2 tUB...

Page 650: ...D tBSD tAS1 tAS1 tAS1 tRSD1 tRSD1 tAC5 tAA2 tRSD1 tWRD2 tWSW1 tWDH1 tWDD tWRD2 tAH1 tAC2 tRDS2 tRDH2 tAA3 tRSD2 tRDS1 tRDH1 tAH1 tASD tASD tRWD tRWD tRWD tRWD B A23 to A0 CS7 to CS0 AS RD D15 to D0 RD...

Page 651: ...1 tRSD2 tRDS2 tRDH2 tASD tASD tRSD1 tRSD1 tAC6 tAC4 tAA5 tAS2 tWDD tWSW2 tWDH1 tWDS1 tWRD1 tWRD2 tAH1 tAA4 tAS1 tAS1 tRWD tCSD1 tRWD tRWD tBSD tBSD tRWD tRWD tRWD B A23 to A0 CS7 to CS0 AS BS RD WR RD...

Page 652: ...2007 Page 630 of 666 REJ09B0311 0200 T1 B A23 to A0 CS7 to CS0 AS BS RD WR RD D15 to D0 RD D15 to D0 LHWR LLWR D15 to D0 WAIT tWTS tWTH tWTS tWTH T2 Tw T3 Read RDNn 1 Read RDNn 0 Write RD WR RD WR Fig...

Page 653: ...tAH3 tWDH3 tWSW1 tWDS2 tWDD tAS3 tWRD2 tWRD2 tRSD2 tRSD1 tAC2 tRDS2 tRDH2 tAS3 tRSD1 tAH3 tAH1 tASD T1 T2 Tt tRWD tRWD tRWD tBSD tBSD tRWD tRWD tRWD B A23 to A0 CS7 to CS0 AS RD D15 to D0 RD D15 to D...

Page 654: ...H2 tAH3 tWDH3 tWSW2 tWDS3 tAS4 tAS3 tRSD1 tWDD tWRD2 tWRD1 tAC4 tRDS2 tRDH2 tRSD2 tAC6 tRDS1 tRDH1 T1 T2 T3 Tt AS RD RD BS RD WR RD WR RD WR tRWD tRWD tRWD tRWD tRWD tBSD tBSD tRWD B A23 to A0 CS7 to...

Page 655: ...AS BS RD WR tAD tCSD1 tAS1 tAH1 tAH1 tASD tASD T2 tBSD tAC5 tAC5 tAA2 tRWD tRWD tBSD RD RD WR RD tRSD1 tRSD1 tRDS1 tRDH1 tUBW1 tUBD tRWD tWDD tWDH1 tRWD tUBD tAS1 tAS1 B A23 to A0 CS7 to CS0 Read D15...

Page 656: ...tAD tCSD1 tAS1 tAH1 tASD tRWD tRWD tASD AS BS RD WR RD RD WR RD T2 T3 tAS1 tAH1 tAS1 tRSD1 tUBD tRWD tWDD tWDH1 tRWD tUBD tRSD1 tRDS1 tAC6 tAC6 tUBW2 tAA4 tRDH1 tBSD tBSD B A23 to A0 CS7 to CS0 LUB LL...

Page 657: ...ics Rev 2 00 Jun 28 2007 Page 635 of 666 REJ09B0311 0200 T1 B A23 to A6 A0 A5 to A1 CS7 to CS0 AS BS RD WR RD D15 to D0 LHWR LLWR T2 T1 tAD tRSD2 tAA1 tRDS2 tRDH2 T1 Read High Figure 20 15 Burst ROM A...

Page 658: ...0 Jun 28 2007 Page 636 of 666 REJ09B0311 0200 T1 B A23 to A6 A0 A5 to A1 CS7 to CS0 AS RD D15 to D0 High LHWR LLWR T2 T3 T1 tAD tAS1 tASD tAA3 tRSD2 tRDS2 tRDH2 tASD tAH1 T2 Read BS RD WR Figure 20 16...

Page 659: ...9B0311 0200 Tma1 tAD tAHD tAHW1 tWSW1 tAHD tMAD1 tMAH tRDS2 tRDH2 Tma2 T1 T2 RD WR BS RD RD WR tMAD1 tWDD tWDH1 tMAS1 tMAH tMAS1 B A23 to A0 CS7 to CS0 AH AS D15 to D0 LHWR LLWR D15 to D0 Read Write F...

Page 660: ...WAIT tAD tAHD tAHD tAHW2 tMAS2 tMAH RD RD WR tMAD1 tRDS2 tRDH2 tWDD tWDS1 tWTS tWTH tWTS tWTH tWDH1 tMAS2 tMAH tMAD1 A23 to A0 CS7 to CS0 AH AS D15 to D0 Read Write D15 to D0 LHWR LLWR B Figure 20 18...

Page 661: ...28 2007 Page 639 of 666 REJ09B0311 0200 B BREQ tBREQS tBREQS tBACD tBZD tBACD tBZD BACK A23 to A0 CS7 to CS0 D15 to D0 AS RD LHWR LLWR Figure 20 19 External Bus Release Timing B BACK tBRQOD tBRQOD BRE...

Page 662: ...Figure 20 22 Timer input setup time tTICS 25 ns Timer clock input setup time tTCKS 25 ns Figure 20 23 Timer clock pulse width Single edge setting tTCKWH 1 5 tcyc Both edge setting tTCKWL 2 5 tcyc PPG...

Page 663: ...ked synchronous tRXH 40 ns A D converter Trigger input setup time tTRGS 30 ns Figure 20 31 T1 tPRS tPRH tPWD T2 P Ports 1 to 3 5 6 A B D to F H I read Ports 1 to 3 6 A B D to F H I write Figure 20 21...

Page 664: ...0 tPOD Figure 20 24 PPG Output Timing P TMO0 to TMO3 tTMOD Figure 20 25 8 Bit Timer Output Timing P TMRI0 to TMRI3 tTMRS Figure 20 26 8 Bit Timer Reset Input Timing P TMCI0 to TMCI3 tTMCWL tTMCWH tTMC...

Page 665: ...SCK2 SCK4 tSCKW tSCKr tSCKf tScyc Figure 20 29 SCK Clock Input Timing SCK0 to SCK2 SCK4 tTXD tRXS tRXH TxD0 to TxD2 TxD4 transmit data RxD0 to RxD2 RxD4 receive data Figure 20 30 SCI Input Output Timi...

Page 666: ...V to 3 6 V Vref 3 0 V to AVCC VSS AVSS 0 V P 8 MHz to 35 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Item Min Typ Max Unit Resolution 10 10 10 Bit Conversion t...

Page 667: ...tics Conditions VCC 3 0 V to 3 6 V AVCC 3 0 V to 3 6 V Vref 3 0 V to AVCC VSS AVSS 0 V P 8 MHz to 35 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Item Min Typ M...

Page 668: ...Section 20 Electrical Characteristics Rev 2 00 Jun 28 2007 Page 646 of 666 REJ09B0311 0200...

Page 669: ...DA0 IRQ6 B All Hi Z Hi Z DAOE0 1 Keep DAOE0 0 Hi Z DAOE0 1 Keep DAOE0 0 Hi Z Keep P57 AN7 DA1 IRQ7 B All Hi Z Hi Z DAOE1 1 Keep DAOE1 0 Hi Z DAOE1 1 Keep DAOE1 0 Hi Z Keep P65 to P60 All Hi Z Hi Z Ke...

Page 670: ...LHWR LUB output Hi Z Other than above Keep PA5 RD External extended mode H Hi Z H Hi Z Hi Z PA6 AS AH BS B External extended mode H Hi Z AS BS output H AH output L Other than above Keep AS AH BS outpu...

Page 671: ...nal extended mode L Hi Z Keep Hi Z Hi Z PF0 to PF4 External extended mode L Hi Z Keep Address output Hi Z Other than above Keep Address output Hi Z Other than above Keep PF5 CS5 D PF6 CS6 D PF7 CS4 C...

Page 672: ...ix Rev 2 00 Jun 28 2007 Page 650 of 666 REJ09B0311 0200 B Product Lineup Product Classification Product Model Marking Package Package Code H8SX 1650C ROMless R5S61650CFPV R5S61650CFPV PLQP0120LA A FP...

Page 673: ...A 1 L L 1 2 3 1 F 120 91 90 61 60 31 30 1 x Index mark y D H D b p E H E Z D Z E 1 0 0 125 0 16 1 2 1 2 0 07 0 20 0 145 0 09 0 23 0 18 0 13 Max Nom Min Dimension in Millimeters Symbol Reference 14 1 1...

Page 674: ...t 1 Port 2 Port 3 Port 6 PA2 to PA0 PB3 to PB0 PF7 to PF5 Connect each pin to VCC via a pull up resistor or to VSS via a pull down resistor Port 5 Connect each pin to AVCC via a pull up resistor or to...

Page 675: ...rt I Used as a data bus Since this is a general purpose input port in its initial state connect each pin to VCC via a pull up resistor or connect each pin to VSS via a pull down resistor Vref Connect...

Page 676: ...Appendix Rev 2 00 Jun 28 2007 Page 654 of 666 REJ09B0311 0200...

Page 677: ...lowing additions and changes have been made in the switch from the H8SX 1650A to the H8SX 1650C The chip select signal is added to PF7 PF6 and PF5 Table 1 1 Overview of Functions 6 Modified Classifica...

Page 678: ...5 PA7 P C P C PA6 PA4 P C P C Port A PA2 to PA0 P C P C PB3 to 1 P C P C Port B PB0 P C P C Figure 3 1 Address Map Advanced Mode 68 Deleted Notes In the H8SX 1650 space from H FFC000 to H FF6000 was s...

Page 679: ...oller CS4 A output 1 8 2 10 Port F 1 PF7 A23 CS4 C CS5 C CS6 C CS7 C 283 Added Setting I O Port Module Name Pin Function A23_ OE CS4 C output CS5 C output CS6 C output CS7 C output A23 output 1 CS4 C...

Page 680: ...Signals and Settings in Each Port 290 291 Modified Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings PB 0 CS4A_OE CS4 PFCR1 CS 4S...

Page 681: ...pin PF7 as CS5 C output 11 Specifies pin PF5 as CS5 D output 1 0 CS4SA CS4SB CS4 Output Pin Select Selects the output pin for CS4 when CS4 output is enabled CS4E 1 00 Specifies pin PB0 as CS4 A output...

Page 682: ...ate PB0 CS0 CS4 A CS5 B External extended mode H Hi Z CS output H Other than above Keep CS output Hi Z Other than above Keep PF0 to PF4 External extended mode L Hi Z Keep Address output Hi Z Other tha...

Page 683: ...tings in each port 287 Average transfer rate generator 450 B B clock output control 585 Basic bus interface 157 167 Big endian 156 Bit rate 471 Block diagram 8 Block transfer mode 239 Burst ROM interf...

Page 684: ...ress mode 228 Full scale error 538 G General registers 25 H Hardware standby mode 564 580 I I O ports 251 ID code 492 Idle cycle 198 Illegal instruction 81 Index register 25 Initial register values 29...

Page 685: ...wer down states 563 Processing states 59 Product lineup 650 Program execution state 59 Program stop state 59 Programmable pulse generator PPG 389 Pull up MOS control register 261 Q Quantization error...

Page 686: ...592 602 611 RDNCR 132 590 599 609 RDR 454 594 603 612 RSR 454 RSTCSR 441 594 604 613 SAR 223 SBR 28 SBYCR 566 590 600 609 SCKCR 554 590 600 609 SCMR 470 594 603 612 SCR 458 594 603 612 SEMR 479 590 6...

Page 687: ...System clock I 146 553 T Toggle output 349 Trace exception handling 75 Transfer information 228 Transfer information read skip function 235 Transfer information writeback skip function 236 Transmit r...

Page 688: ...Rev 2 00 Jun 28 2007 Page 666 of 666 REJ09B0311 0200...

Page 689: ...n Date Rev 1 00 Mar 28 2006 Rev 2 00 Jun 28 2007 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solu...

Page 690: ...Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co L...

Page 691: ......

Page 692: ...H8SX 1650 Group Hardware Manual...

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