Renesas H8SX/1650, Hardware Manual

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Section 19 List of Registers
Rev.2.00 Jun. 28, 2007 Page 587 of 666
REJ09B0311-0200
Section 19 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
•
Registers are listed from the lower allocation addresses.
•
Registers are classified according to functional modules.
•
The number of Access Cycles indicates the number of states based on the specified reference
clock. For details, see section 6.12.1, Access to Internal Address Space.
•
Undefined and reserved addresses cannot be accessed. Do not access these addresses;
otherwise, the operation when accessing these bits and subsequent operations cannot be
guaranteed.
2. Register bits
•
Bit configurations of the registers are listed in the same order as the register addresses.
•
Reserved bits are indicated by

in the bit name column.
•
Space in the bit name field indicates that the entire register is allocated to either the counter or
data.
•
For the registers of 16 or 32 bits, the MSB is listed first.
Byte configuration description order is subject to big endian.
3. Register states in each operating mode
•
Register states are listed in the same order as the register addresses.
•
For the initialized state of each bit, refer to the register description in the corresponding
section.
•
The register states shown here are for the basic operating modes. If there is a specific reset for
an on-chip peripheral module, refer to the section on that on-chip peripheral module.